|
| 1 | +test optimize precise-output |
| 2 | +set opt_level=speed |
| 3 | +target x86_64 |
| 4 | + |
| 5 | +;; `brif (ctz X)` / `brif (clz X)` — 2-op forms with no `icmp ne 0` |
| 6 | +;; interposed for the value-level rules in `opts/icmp.isle` to hinge on. |
| 7 | +;; The new `simplify_skeleton` rule rewrites the brif's cond operand |
| 8 | +;; in place via `ReplaceBranchCond`; successors are preserved so the |
| 9 | +;; CFG is unchanged. |
| 10 | + |
| 11 | +;; `brif (ctz X)` branches when `ctz(X) != 0`, i.e. LSB(X) == 0. |
| 12 | +function %brif_ctz_i32(i32) -> i32 { |
| 13 | +block0(v0: i32): |
| 14 | + v1 = ctz v0 |
| 15 | + brif v1, block1, block2 |
| 16 | + |
| 17 | +block1: |
| 18 | + v2 = iconst.i32 100 |
| 19 | + return v2 |
| 20 | + |
| 21 | +block2: |
| 22 | + v3 = iconst.i32 200 |
| 23 | + return v3 |
| 24 | +} |
| 25 | + |
| 26 | +; function %brif_ctz_i32(i32) -> i32 fast { |
| 27 | +; block0(v0: i32): |
| 28 | +; v4 = iconst.i32 1 |
| 29 | +; v5 = band v0, v4 ; v4 = 1 |
| 30 | +; v6 = iconst.i32 0 |
| 31 | +; v7 = icmp eq v5, v6 ; v6 = 0 |
| 32 | +; brif v7, block1, block2 |
| 33 | +; |
| 34 | +; block1: |
| 35 | +; v2 = iconst.i32 100 |
| 36 | +; return v2 ; v2 = 100 |
| 37 | +; |
| 38 | +; block2: |
| 39 | +; v3 = iconst.i32 200 |
| 40 | +; return v3 ; v3 = 200 |
| 41 | +; } |
| 42 | + |
| 43 | +;; `brif (clz X)` branches when `clz(X) != 0`, i.e. MSB(X) == 0. |
| 44 | +function %brif_clz_i32(i32) -> i32 { |
| 45 | +block0(v0: i32): |
| 46 | + v1 = clz v0 |
| 47 | + brif v1, block1, block2 |
| 48 | + |
| 49 | +block1: |
| 50 | + v2 = iconst.i32 100 |
| 51 | + return v2 |
| 52 | + |
| 53 | +block2: |
| 54 | + v3 = iconst.i32 200 |
| 55 | + return v3 |
| 56 | +} |
| 57 | + |
| 58 | +; function %brif_clz_i32(i32) -> i32 fast { |
| 59 | +; block0(v0: i32): |
| 60 | +; v4 = iconst.i32 0 |
| 61 | +; v5 = icmp sge v0, v4 ; v4 = 0 |
| 62 | +; brif v5, block1, block2 |
| 63 | +; |
| 64 | +; block1: |
| 65 | +; v2 = iconst.i32 100 |
| 66 | +; return v2 ; v2 = 100 |
| 67 | +; |
| 68 | +; block2: |
| 69 | +; v3 = iconst.i32 200 |
| 70 | +; return v3 ; v3 = 200 |
| 71 | +; } |
| 72 | + |
| 73 | +;; Same for i64. |
| 74 | +function %brif_ctz_i64(i64) -> i32 { |
| 75 | +block0(v0: i64): |
| 76 | + v1 = ctz v0 |
| 77 | + brif v1, block1, block2 |
| 78 | + |
| 79 | +block1: |
| 80 | + v2 = iconst.i32 100 |
| 81 | + return v2 |
| 82 | + |
| 83 | +block2: |
| 84 | + v3 = iconst.i32 200 |
| 85 | + return v3 |
| 86 | +} |
| 87 | + |
| 88 | +; function %brif_ctz_i64(i64) -> i32 fast { |
| 89 | +; block0(v0: i64): |
| 90 | +; v4 = iconst.i64 1 |
| 91 | +; v5 = band v0, v4 ; v4 = 1 |
| 92 | +; v6 = iconst.i64 0 |
| 93 | +; v7 = icmp eq v5, v6 ; v6 = 0 |
| 94 | +; brif v7, block1, block2 |
| 95 | +; |
| 96 | +; block1: |
| 97 | +; v2 = iconst.i32 100 |
| 98 | +; return v2 ; v2 = 100 |
| 99 | +; |
| 100 | +; block2: |
| 101 | +; v3 = iconst.i32 200 |
| 102 | +; return v3 ; v3 = 200 |
| 103 | +; } |
| 104 | + |
| 105 | +function %brif_clz_i64(i64) -> i32 { |
| 106 | +block0(v0: i64): |
| 107 | + v1 = clz v0 |
| 108 | + brif v1, block1, block2 |
| 109 | + |
| 110 | +block1: |
| 111 | + v2 = iconst.i32 100 |
| 112 | + return v2 |
| 113 | + |
| 114 | +block2: |
| 115 | + v3 = iconst.i32 200 |
| 116 | + return v3 |
| 117 | +} |
| 118 | + |
| 119 | +; function %brif_clz_i64(i64) -> i32 fast { |
| 120 | +; block0(v0: i64): |
| 121 | +; v4 = iconst.i64 0 |
| 122 | +; v5 = icmp sge v0, v4 ; v4 = 0 |
| 123 | +; brif v5, block1, block2 |
| 124 | +; |
| 125 | +; block1: |
| 126 | +; v2 = iconst.i32 100 |
| 127 | +; return v2 ; v2 = 100 |
| 128 | +; |
| 129 | +; block2: |
| 130 | +; v3 = iconst.i32 200 |
| 131 | +; return v3 ; v3 = 200 |
| 132 | +; } |
0 commit comments