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make stm fetch instr early unless reg list is empty
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cores/gba/rtl/cpu/ControlUnit.sv

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -770,7 +770,10 @@ module GBA_ControlUnit (
770770

771771
// First cycle: Prefetch and calculate first address
772772
if (cycle == 8'd0) begin
773-
if (decoder_bus.instr_type == ARM_INSTR_LDM) begin
773+
if (decoder_bus.instr_type == ARM_INSTR_STM && regs_count != 0) begin
774+
$display("[ControlUnit] Cycle 0 of STM instruction, calculating address");
775+
control_signals |= fetch_instr_early();
776+
end else if (decoder_bus.instr_type == ARM_INSTR_LDM) begin
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$display("[ControlUnit] Cycle 0 of LDM instruction, calculating address");
775778
control_signals |= fetch_instr_early();
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end
@@ -1099,7 +1102,9 @@ module GBA_ControlUnit (
10991102
// from memory and latch it to the fetched IR
11001103
if (cycle == 8'd1 + 8'(regs_count)) begin
11011104

1102-
control_signals |= fetch_next_instr();
1105+
// control_signals |= fetch_next_instr();
1106+
1107+
control_signals.memory_advance_early_fetched_IR = 1'b1;
11031108
// control_signals.incrementer_writeback = 1'b1;
11041109

11051110
control_signals.Rp_imm =

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