implement BX instruction

Author: evanwporter

.github/workflows/gba.yaml

@@ -66,17 +66,18 @@ jobs:
       fail-fast: true
       matrix:
         test:
-          - data_proc_immediate
-          - data_proc_immediate_shift
-          - data_proc_register_shift
-          - ldm_stm
-          - ldr_str_immediate_offset
-          - ldr_str_register_offset
-          - ldrh_strh
-          - ldrsb_ldrsh
-          - b_bl
-          - swi
-          - mul_mla
+          - arm_data_proc_immediate
+          - arm_data_proc_immediate_shift
+          - arm_data_proc_register_shift
+          - arm_ldm_stm
+          - arm_ldr_str_immediate_offset
+          - arm_ldr_str_register_offset
+          - arm_ldrh_strh
+          - arm_ldrsb_ldrsh
+          - arm_b_bl
+          - arm_bx
+          - arm_swi
+          - arm_mul_mla
 
     steps:
       - uses: actions/checkout@v4
@@ -89,4 +90,4 @@ jobs:
 
       - name: Run GBA tests
         run: |
-          .\test_gba.exe --gtest_filter=*arm_${{ matrix.test }}_json --test-dir=${{ github.workspace }}/tests/
+          .\test_gba.exe --gtest_filter=*${{ matrix.test }}_json --test-dir=${{ github.workspace }}/tests/

cores/gba/rtl/cpu/CPU.sv

@@ -29,6 +29,9 @@ module ARM7TMDI (
   /// Data that has been latched from the read bus
   word_t read_data;
 
+  execution_mode_t execution_mode;
+  assign execution_mode = execution_mode_t'(regs.CPSR[5]);
+
   always_comb begin
     if (control_signals.exception != EXCEPTION_NONE) begin
       // TODO: think about combining with `update_cspr_mode`
@@ -378,11 +381,20 @@ module ARM7TMDI (
           $display("Setting flush_req_pending to ensure flush on next cycle.");
         end
       end else if (control_signals.incrementer_writeback) begin
-        // PC = PC + 4
+        unique case (execution_mode)
+          MODE_ARM: begin
+            // PC = PC + 4
 
-        `WRITE_REG(regs, cpu_mode, 15, read_reg(regs, cpu_mode, 15) + 32'd4)
-        $display("Incrementing PC to: %0d", read_reg(regs, cpu_mode, 15) + 32'd4);
-        $fflush();
+            `WRITE_REG(regs, cpu_mode, 15, read_reg(regs, cpu_mode, 15) + 32'd4)
+            $display("Incrementing PC to: %0d", read_reg(regs, cpu_mode, 15) + 32'd4);
+            $fflush();
+          end
+          MODE_THUMB: begin
+            `WRITE_REG(regs, cpu_mode, 15, read_reg(regs, cpu_mode, 15) + 32'd2)
+            $display("Incrementing PC to: %0d", read_reg(regs, cpu_mode, 15) + 32'd2);
+            $fflush();
+          end
+        endcase
       end
 
       $display("[CPU] Checking ALU flags writeback. ALU_set_flags=%b, restore_cpsr_from_spsr=%b",
@@ -393,6 +405,13 @@ module ARM7TMDI (
         $display("Restoring CPSR from SPSR_%0d: 0x%08x", cpu_mode, read_spsr(regs, cpu_mode));
       end
 
+      if (control_signals.set_thumb_mode) begin
+        regs.CPSR[5] <= B_bus[0];
+        `WRITE_REG(regs, cpu_mode, 4'd15, B_bus & 32'hFFFFFFFE)
+        flush_req <= 1'b1;
+        $display("Setting Thumb mode bit in CPSR");
+      end
+
       if (control_signals.ALU_set_flags && control_signals.pipeline_advance) begin
 
         if ((decoder_bus.word.Rd == 4'd15) && mode_has_spsr(
@@ -452,7 +471,6 @@ module ARM7TMDI (
           `WRITE_REG(regs, control_signals.force_user_mode ? CPU_MODE_USR : cpu_mode,
                      decoder_bus.word.Rn, alu_bus.result)
         end
-        ALU_WB_REG_14: `WRITE_REG(regs, cpu_mode, 14, alu_bus.result)
         ALU_WB_REG_RP: begin
           `WRITE_REG(regs, control_signals.force_user_mode ? CPU_MODE_USR : cpu_mode,
                      control_signals.Rp_imm, alu_bus.result)
@@ -486,7 +504,15 @@ module ARM7TMDI (
         end
 
         ADDR_SRC_INCR: begin
-          bus.addr <= bus.addr + 32'd4;
+          unique case (execution_mode)
+            MODE_ARM: begin
+              bus.addr <= bus.addr + 32'd4;
+            end
+            MODE_THUMB: begin
+              bus.addr <= bus.addr + 32'd2;
+              $display("Incrementing address bus for Thumb mode: new addr=%0d", bus.addr);
+            end
+          endcase
         end
       endcase
     end

cores/gba/rtl/cpu/ControlUnit.sv

@@ -1016,7 +1016,7 @@ module ControlUnit (
         end
 
         // ============================
-        // Branch & Branch with Link
+        // Branch
         // ============================
 
         ARM_INSTR_BRANCH: begin
@@ -1075,6 +1075,22 @@ module ControlUnit (
           end
         end
 
+        ARM_INSTR_BRANCH_EX: begin
+          if (cycle == 8'd0) begin
+            control_signals.ALU_op = ALU_OP_MOV;
+            control_signals.addr_bus_src = ADDR_SRC_ALU;
+
+            // control_signals.ALU_writeback = ALU_WB_REG_RP;
+            // control_signals.Rp_imm = 4'd15;
+
+            control_signals.B_bus_source = B_BUS_SRC_REG_RN;
+
+            control_signals.set_thumb_mode = 1'b1;
+
+            control_signals.pipeline_advance = 1'b1;
+          end
+        end
+
         ARM_INSTR_SWI: begin
           if (cycle == 8'd0) begin
             // Rd should be R14 (LR)

cores/gba/rtl/cpu/Decoder.sv

@@ -44,6 +44,8 @@ module GBA_Decoder (
     priority casez (IR)
       /// Branch and Branch Exchange
       32'b????_0001_0010_1111_1111_1111_0001_????: begin
+        bus.word.instr_type = ARM_INSTR_BRANCH_EX;
+        bus.word.Rn = IR[3:0];
         $display("[GBA_Decoder] Detected BX instruction with IR=0x%08x", IR);
       end
 

cores/gba/rtl/cpu/control_types.sv

@@ -82,10 +82,7 @@ package gba_control_types_pkg;
     ALU_WB_REG_RN,
 
     /// If set, we need also need to set `Rp_imm`
-    ALU_WB_REG_RP,
-
-    /// Write back to register 14
-    ALU_WB_REG_14
+    ALU_WB_REG_RP
   } alu_writeback_source_t;
 
   typedef struct packed {
@@ -114,6 +111,8 @@ package gba_control_types_pkg;
 
     exception_t exception;
 
+    logic set_thumb_mode;
+
     // ======================================================
     // A Bus
     // ======================================================
@@ -127,8 +126,6 @@ package gba_control_types_pkg;
     // B Bus
     // ======================================================
 
-    /// Hello
-    /// There
     B_bus_source_t B_bus_source;
 
     /// Immediate value to place on the B bus, if selected in `B_bus_source`

cores/gba/rtl/cpu/types.sv

@@ -114,6 +114,11 @@ package gba_cpu_types_pkg;
 
   } cpu_regs_t;
 
+  typedef enum logic {
+    MODE_ARM   = 1'b0,
+    MODE_THUMB = 1'b1
+  } execution_mode_t;
+
   // TODO: figure out priority
   typedef enum logic [2:0] {
     /// No exception