add support for SWI

Author: evanwporter

.github/workflows/gba.yaml

@@ -75,6 +75,7 @@ jobs:
           - arm_ldrh_strh
           - arm_ldrsb_ldrsh
           - arm_b_bl
+          - arm_swi
 
     steps:
       - uses: actions/checkout@v4

cores/gba/resources/Stephen B. Furber - VLSI Risc Architecture and Organization.pdf

@@ -12,7 +12,6 @@ module CPU (
     Bus_if.Master_side bus
 );
 
-  /// TODO: Remove
   control_t control_signals;
 
   word_t IR;
@@ -31,26 +30,40 @@ module CPU (
   word_t read_data;
 
   always_comb begin
-    unique casez (regs.CPSR[4:0])
-
-      5'b0??00: cpu_mode = MODE_USR;  // Old User
-      5'b0??01: cpu_mode = MODE_FIQ;  // Old FIQ
-      5'b0??10: cpu_mode = MODE_IRQ;  // Old IRQ
-      5'b0??11: cpu_mode = MODE_SVC;  // Old Supervisor
-
-      5'b10000: cpu_mode = MODE_USR;  // User
-      5'b10001: cpu_mode = MODE_FIQ;  // FIQ
-      5'b10010: cpu_mode = MODE_IRQ;  // IRQ
-      5'b10011: cpu_mode = MODE_SVC;  // Supervisor
-      5'b10111: cpu_mode = MODE_ABT;  // Abort
-      5'b11011: cpu_mode = MODE_UND;  // Undefined
-      5'b11111: cpu_mode = MODE_SYS;  // System
-
-      default: begin
-        cpu_mode = MODE_USR;
-        $warning("Illegal CPSR mode encoding: %b", regs.CPSR[4:0]);
-      end
-    endcase
+    if (control_signals.exception != EXCEPTION_NONE) begin
+      // TODO: think about combining with `update_cspr_mode`
+      unique case (control_signals.exception)
+        EXCEPTION_NONE: cpu_mode = CPU_MODE_USR;  // Impossible to reach
+        EXCEPTION_RESET: cpu_mode = CPU_MODE_USR;  // TODO;
+        EXCEPTION_UNDEFINED: cpu_mode = CPU_MODE_UND;
+        EXCEPTION_SWI: cpu_mode = CPU_MODE_SVC;
+        EXCEPTION_PABT: cpu_mode = CPU_MODE_ABT;
+        EXCEPTION_DABT: cpu_mode = CPU_MODE_ABT;
+        EXCEPTION_IRQ: cpu_mode = CPU_MODE_IRQ;
+        EXCEPTION_FIQ: cpu_mode = CPU_MODE_FIQ;
+      endcase
+    end else begin
+      unique casez (regs.CPSR[4:0])
+
+        5'b0??00: cpu_mode = CPU_MODE_USR;  // Old User
+        5'b0??01: cpu_mode = CPU_MODE_FIQ;  // Old FIQ
+        5'b0??10: cpu_mode = CPU_MODE_IRQ;  // Old IRQ
+        5'b0??11: cpu_mode = CPU_MODE_SVC;  // Old Supervisor
+
+        5'b10000: cpu_mode = CPU_MODE_USR;  // User
+        5'b10001: cpu_mode = CPU_MODE_FIQ;  // FIQ
+        5'b10010: cpu_mode = CPU_MODE_IRQ;  // IRQ
+        5'b10011: cpu_mode = CPU_MODE_SVC;  // Supervisor
+        5'b10111: cpu_mode = CPU_MODE_ABT;  // Abort
+        5'b11011: cpu_mode = CPU_MODE_UND;  // Undefined
+        5'b11111: cpu_mode = CPU_MODE_SYS;  // System
+
+        default: begin
+          cpu_mode = CPU_MODE_USR;
+          $warning("Illegal CPSR mode encoding: %b", regs.CPSR[4:0]);
+        end
+      endcase
+    end
   end
 
   Decoder_if decoder_bus (
@@ -195,7 +208,7 @@ module CPU (
       B_BUS_SRC_REG_RP: begin
         $display("Driving B bus with value from Rp (R%0d): %0d", control_signals.Rp_imm, read_reg(
                  regs, cpu_mode, control_signals.Rp_imm));
-        B_bus = read_reg(regs, control_signals.force_user_mode ? MODE_USR : cpu_mode,
+        B_bus = read_reg(regs, control_signals.force_user_mode ? CPU_MODE_USR : cpu_mode,
                          control_signals.Rp_imm);
       end
     endcase
@@ -365,6 +378,21 @@ module CPU (
         end
       end
 
+      if (control_signals.exception != EXCEPTION_NONE) begin
+        `WRITE_SPSR(regs, cpu_mode, regs.CPSR)
+
+        regs.user.r15 <= VECTOR_TABLE[control_signals.exception];
+
+        regs.CPSR[7] <= 1'b1;  // Disable IRQ
+
+        regs.CPSR[4:0] <= update_cspr_mode(control_signals.exception);
+
+        flush_req <= 1'b1;
+
+        $display("Performing CPU exception handling from %0d to %0d", cpu_mode,
+                 control_signals.exception);
+      end
+
       unique case (control_signals.ALU_writeback)
         ALU_WB_NONE:   ;
         ALU_WB_REG_RD: begin
@@ -374,12 +402,12 @@ module CPU (
         ALU_WB_REG_RS: `WRITE_REG(regs, cpu_mode, decoder_bus.word.Rs, alu_bus.result)
         ALU_WB_REG_RN: begin
           $display("Writing back ALU result %0d to Rn (R%d)", alu_bus.result, decoder_bus.word.Rn);
-          `WRITE_REG(regs, control_signals.force_user_mode ? MODE_USR : cpu_mode,
+          `WRITE_REG(regs, control_signals.force_user_mode ? CPU_MODE_USR : cpu_mode,
                      decoder_bus.word.Rn, alu_bus.result)
         end
         ALU_WB_REG_14: `WRITE_REG(regs, cpu_mode, 14, alu_bus.result)
         ALU_WB_REG_RP: begin
-          `WRITE_REG(regs, control_signals.force_user_mode ? MODE_USR : cpu_mode,
+          `WRITE_REG(regs, control_signals.force_user_mode ? CPU_MODE_USR : cpu_mode,
                      control_signals.Rp_imm, alu_bus.result)
         end
       endcase

cores/gba/resources/arm7tmdi_data_sheet.pdf

@@ -894,15 +894,16 @@ module ControlUnit (
         ARM_INSTR_BRANCH_LINK: begin
           if (cycle == 8'd0) begin
             // Rd should be R14 (LR)
-            control_signals.ALU_writeback = ALU_WB_REG_14;
+            control_signals.ALU_writeback = ALU_WB_REG_RD;
 
             control_signals.ALU_op = ALU_OP_SUB;
             control_signals.A_bus_source = A_BUS_SRC_RN;
 
             control_signals.B_bus_source = B_BUS_SRC_IMM;
             control_signals.B_bus_imm = 24'd4;
 
-            $display("[ControlUnit] Branch with Link instruction, writing return address to R14");
+            $display("[ControlUnit] Branch with Link instruction, writing return address to R%0d",
+                     decoder_bus.word.Rd);
           end
 
           if (cycle == 8'd1) begin
@@ -923,6 +924,27 @@ module ControlUnit (
             control_signals.pipeline_advance = 1'b1;
           end
         end
+
+        ARM_INSTR_SWI: begin
+          if (cycle == 8'd0) begin
+            // Rd should be R14 (LR)
+            control_signals.ALU_writeback = ALU_WB_REG_RD;
+
+            control_signals.ALU_op = ALU_OP_SUB;
+            control_signals.A_bus_source = A_BUS_SRC_RN;
+
+            control_signals.B_bus_source = B_BUS_SRC_IMM;
+            control_signals.B_bus_imm = 24'd4;
+
+            control_signals.exception = EXCEPTION_SWI;
+
+            $display(
+                "[ControlUnit] Software Interrupt instruction, writing return address to R%0d and preparing for exception handling",
+                decoder_bus.word.Rd);
+
+            control_signals.pipeline_advance = 1'b1;
+          end
+        end
         default: ;
       endcase
     end

cores/gba/rtl/cpu/CPU.sv

@@ -90,6 +90,14 @@ module Decoder (
 
       /// Software Interrupt
       32'b????_1111_????_????_????_????_????_????: begin
+        // TODO: Decode comments from ARM SWI IR.
+
+        bus.word.instr_type = ARM_INSTR_SWI;
+
+        // Overwrite Rn and Rd
+        bus.word.Rn = 4'd15;
+        bus.word.Rd = 4'd14;
+
         $display("[Decoder] Detected SWI instruction with IR=0x%08x", IR);
       end
 

cores/gba/rtl/cpu/ControlUnit.sv

@@ -110,6 +110,11 @@ package control_types_pkg;
     /// TODO: Refactor
     logic restore_cpsr_from_spsr;
 
+    // TODO: Refactor
+    set_cpu_mode_t set_mode;
+
+    exception_t exception;
+
     // ======================================================
     // Shift Bus
     // ======================================================

cores/gba/rtl/cpu/Decoder.sv

@@ -88,6 +88,7 @@ package cpu_types_pkg;
     /**
       From: https://mgba-emu.github.io/gbatek/#current-program-status-register-cpsr
       
+      ```plain
       Bit   Expl.
       31    N - Sign Flag       (0=Not Signed, 1=Signed)               ;\
       30    Z - Zero Flag       (0=Not Zero, 1=Zero)                   ; Condition
@@ -99,6 +100,7 @@ package cpu_types_pkg;
       6     F - FIQ disable     (0=Enable, 1=Disable)                     ; Control
       5     T - State Bit       (0=ARM, 1=THUMB) - Do not change manually!; Bits
       4-0   M4-M0 - Mode Bits   (See below)         
+      ```
     */
     word_t CPSR;
 
@@ -112,14 +114,92 @@ package cpu_types_pkg;
 
   } cpu_regs_t;
 
-  typedef enum logic [3:0] {
-    MODE_USR = 4'b0000,
-    MODE_FIQ = 4'b0001,
-    MODE_IRQ = 4'b0010,
-    MODE_SVC = 4'b0011,
-    MODE_ABT = 4'b0111,
-    MODE_UND = 4'b1011,
-    MODE_SYS = 4'b1111
+  // TODO: figure out priority
+  typedef enum logic [2:0] {
+    /// No exception
+    EXCEPTION_NONE = 3'd0,
+
+    /// Reset
+    EXCEPTION_RESET = 3'd1,
+
+    /// Undefined instruction (attempting to execute an undefined / illegal instruction)
+    EXCEPTION_UNDEFINED = 3'd2,
+
+    /// Software Interrupt (SWI)
+    EXCEPTION_SWI = 3'd3,
+
+    /// Prefetch abort (fetching instruction from memory failed)
+    EXCEPTION_PABT = 3'd4,
+
+    /// Data abort (data access from memory failed)
+    EXCEPTION_DABT = 3'd5,
+
+    /// Interrupt Request (IRQ)
+    EXCEPTION_IRQ = 3'd6,
+
+    /// Fast Interrupt Request (FIQ)
+    EXCEPTION_FIQ = 3'd7
+  } exception_t;
+
+  localparam logic [31:0] VECTOR_TABLE[0:7] = '{
+      32'hXXXX_XXXX,  // NONE (illegal / unused)
+      32'h0000_0000,  // RESET
+      32'h0000_0004,  // UNDEFINED
+      32'h0000_0008,  // SWI
+      32'h0000_000C,  // PREFETCH_ABORT
+      32'h0000_0010,  // DATA_ABORT
+      32'h0000_0018,  // IRQ
+      32'h0000_001C  // FIQ
+  };
+
+  typedef enum logic [2:0] {
+
+    SET_CPU_MODE_NONE = 3'b000,
+
+    /// User mode (USR)
+    SET_CPU_MODE_USR,
+
+    /// Fast Interrupt Request mode (FIQ)
+    SET_CPU_MODE_FIQ,
+
+    /// Interrupt Request mode (IRQ)
+    SET_CPU_MODE_IRQ,
+
+    /// Supervisor mode (SVC)
+    SET_CPU_MODE_SVC,
+
+    /// Abort mode (ABT)
+    SET_CPU_MODE_ABT,
+
+    /// Undefined mode (UND)
+    SET_CPU_MODE_UND,
+
+    /// System mode (SYS)
+    SET_CPU_MODE_SYS
+  } set_cpu_mode_t;
+
+  typedef enum logic [2:0] {
+
+    /// User mode (USR)
+    CPU_MODE_USR,
+
+    /// Fast Interrupt Request mode (FIQ)
+    CPU_MODE_FIQ,
+
+    /// Interrupt Request mode (IRQ)
+    CPU_MODE_IRQ,
+
+    /// Supervisor mode (SVC)
+    CPU_MODE_SVC,
+
+    /// Abort mode (ABT)
+    CPU_MODE_ABT,
+
+    /// Undefined mode (UND)
+    CPU_MODE_UND,
+
+    /// System mode (SYS)
+    CPU_MODE_SYS
   } cpu_mode_t;
 
   typedef enum logic [1:0] {