DO THE THUMB PARTS

evanwporter · evanwporter · commit bbb36e30b94b · 2026-03-26T15:23:21.000-07:00
diff --git a/cores/gba/include/gba/cpu/util.svh b/cores/gba/include/gba/cpu/util.svh
@@ -50,7 +50,6 @@
   $display("shift_type            : %s", ctrl.shift_type.name()); \
   $display("shift_use_rxx         : %0b", ctrl.shift_use_rxx); \
   $display("shift_amount          : %0d", ctrl.shift_amount); \
-  $display("pipeline_flush        : %0b", ctrl.pipeline_flush); \
   $display("pipeline_advance      : %0b", ctrl.pipeline_advance); \
   $display("----------------------"); \
   $fflush();
diff --git a/cores/gba/rtl/cpu/CPU.sv b/cores/gba/rtl/cpu/CPU.sv
@@ -263,6 +263,11 @@ module ARM7TMDI (
     instr_boundary <= control_signals.pipeline_advance;
   end
 
+
+  wire pc_modified = (control_signals.ALU_writeback == ALU_WB_REG_RD && decoder_bus.decoded_regs.Rd == 4'd15) ||
+                     (control_signals.ALU_writeback == ALU_WB_REG_RN && decoder_bus.decoded_regs.Rn == 4'd15) ||
+                     (control_signals.ALU_writeback == ALU_WB_REG_RP && control_signals.Rp_imm == 4'd15);
+
   // ======================================================
   // Memory Module
   // ======================================================
@@ -369,9 +374,7 @@ module ARM7TMDI (
         flush_req <= 1'b1;
       end
 
-      if ((control_signals.ALU_writeback == ALU_WB_REG_RD && decoder_bus.decoded_regs.Rd == 4'd15) ||
-          (control_signals.ALU_writeback == ALU_WB_REG_RN && decoder_bus.decoded_regs.Rn == 4'd15) ||
-          (control_signals.ALU_writeback == ALU_WB_REG_RP && control_signals.Rp_imm == 4'd15)) begin
+      if (pc_modified) begin
 
         $display("ALU writeback to PC (R15) detected. ALU_writeback=%0d, Rd=%0d, Rn=%0d",
                  control_signals.ALU_writeback, decoder_bus.decoded_regs.Rd,
@@ -388,9 +391,8 @@ module ARM7TMDI (
         unique case (execution_mode)
           MODE_ARM: begin
             // PC = PC + 4
-            `WRITE_REG(regs, cpu_mode, 15, read_reg(regs, cpu_mode, 15) + 32'd4, execution_mode,
-                       1'b0)
-            $display("Incrementing PC to: %0d", read_reg(regs, cpu_mode, 15) + 32'd4);
+            `WRITE_REG(regs, cpu_mode, 15, bus.addr + 32'd4, execution_mode, 1'b0)
+            $display("Incrementing PC to: %0d", bus.addr + 32'd4);
             $fflush();
           end
           MODE_THUMB: begin
@@ -492,36 +494,57 @@ module ARM7TMDI (
     end else begin
       $display("[CPU] addr=%0d", bus.addr);
 
-      unique case (control_signals.addr_bus_src)
-        ADDR_SRC_NONE: begin
-          // bus.addr <= 32'd0;
-        end
-
-        ADDR_SRC_ALU: begin
-          $display("[CPU] Driving address bus with ALU result: %0d", alu_bus.result);
+      if (control_signals.pipeline_advance) begin
+        bus.addr <= bus.addr + 32'd4;
+        if (pc_modified) begin
           bus.addr <= alu_bus.result;
+        end else if (flush_req_pending) begin
+          bus.addr <= read_reg(regs, cpu_mode, 15);
+          $display(
+              "Pipeline advance with pending flush request, setting address bus to PC value: 0x%08x",
+              read_reg(regs, cpu_mode, 15));
         end
+      end else begin
 
-        ADDR_SRC_PC: begin
-          $display("Setting address bus to PC value: 0x%08x", read_reg(regs, cpu_mode, 15));
-          unique case (execution_mode)
-            MODE_ARM:   bus.addr <= read_reg(regs, cpu_mode, 15) & ~32'd3;
-            MODE_THUMB: bus.addr <= read_reg(regs, cpu_mode, 15) & ~32'd1;
-          endcase
-        end
+        unique case (control_signals.addr_bus_src)
+          ADDR_SRC_NONE: begin
+            // bus.addr <= 32'd0;
+          end
 
-        ADDR_SRC_INCR: begin
-          unique case (execution_mode)
-            MODE_ARM: begin
-              bus.addr <= bus.addr + 32'd4;
-            end
-            MODE_THUMB: begin
-              bus.addr <= bus.addr + 32'd4;
-              $display("Incrementing address bus for Thumb mode: new addr=%0d", bus.addr);
-            end
-          endcase
-        end
-      endcase
+          ADDR_SRC_ALU: begin
+            $display("[CPU] Driving address bus with ALU result: %0d", alu_bus.result);
+            bus.addr <= alu_bus.result;
+          end
+
+          ADDR_SRC_PC: begin
+            $display("Setting address bus to PC value: 0x%08x", read_reg(regs, cpu_mode, 15));
+            unique case (execution_mode)
+              MODE_ARM:   bus.addr <= read_reg(regs, cpu_mode, 15) & ~32'd3;
+              MODE_THUMB: bus.addr <= read_reg(regs, cpu_mode, 15) & ~32'd1;
+            endcase
+          end
+
+          ADDR_SRC_PC_RESTORE: begin
+            $display("Restoring address bus from PC value: 0x%08x", read_reg(regs, cpu_mode, 15));
+            unique case (execution_mode)
+              MODE_ARM:   bus.addr <= read_reg(regs, cpu_mode, 15) - 32'd4 & ~32'd3;
+              MODE_THUMB: bus.addr <= read_reg(regs, cpu_mode, 15) - 32'd4 & ~32'd1;
+            endcase
+          end
+
+          ADDR_SRC_INCR: begin
+            unique case (execution_mode)
+              MODE_ARM: begin
+                bus.addr <= bus.addr + 32'd4;
+              end
+              MODE_THUMB: begin
+                bus.addr <= bus.addr + 32'd4;
+                $display("Incrementing address bus for Thumb mode: new addr=%0d", bus.addr);
+              end
+            endcase
+          end
+        endcase
+      end
     end
   end
 
diff --git a/cores/gba/rtl/cpu/ControlUnit.sv b/cores/gba/rtl/cpu/ControlUnit.sv
@@ -126,7 +126,7 @@ module GBA_ControlUnit (
     end else if (flush_cnt == 3'd1) begin
       control_signals |= fetch_next_instr();
       control_signals.incrementer_writeback = 1;
-      control_signals.addr_bus_src = ADDR_SRC_PC;
+      control_signals.addr_bus_src = ADDR_SRC_INCR;
       control_signals.pipeline_advance = 1'b1;
 
       $display("[ControlUnit] Flush cycle 2, flushing instruction");
@@ -136,7 +136,7 @@ module GBA_ControlUnit (
       // If the condition check fails, we still want to advance the pipeline and fetch the next instruction
       control_signals |= fetch_next_instr();
       control_signals.incrementer_writeback = 1;
-      control_signals.addr_bus_src = ADDR_SRC_PC;
+      control_signals.addr_bus_src = ADDR_SRC_INCR;
       control_signals.pipeline_advance = 1'b1;
 
       $display(
@@ -762,10 +762,12 @@ module GBA_ControlUnit (
 
           // First cycle: Prefetch and calculate first address
           if (cycle == 8'd0) begin
-            // Perform a prefetch
-            control_signals |= fetch_next_instr();
+            // // Perform a prefetch
+            // control_signals |= fetch_next_instr();
+
+            // // Stash address in PC so we can return later
+            // control_signals.stash_addr = 1'b1;
 
-            // Stash address + 4 in PC so we can return later
             control_signals.incrementer_writeback = 1'b1;
 
             // Update address for next cycle
@@ -962,7 +964,7 @@ module GBA_ControlUnit (
             end else
 
             // Optionally writeback address to Rn and 
-            // fetch first first word from memory
+            // write first first word to memory
             if (cycle == 8'd1) begin
               control_signals.Rp_imm =
                   get_ith_bit(4'(cycle - 8'd1), decoder_bus.word.arm.block.reg_list);
@@ -996,9 +998,9 @@ module GBA_ControlUnit (
                   "[ControlUnit] Cycle 1 of STM instruction, address calculation done, preparing for memory write");
             end else
 
-            // Latch the last fetched word into the register file and 
+            // Write the current register into memory and 
             // increment address for the next memory access
-            if (cycle < 8'd1 + 8'(regs_count)) begin
+            if (cycle < 8'(regs_count)) begin
               control_signals.Rp_imm =
                   get_ith_bit(4'(cycle - 8'd1), decoder_bus.word.arm.block.reg_list);
 
@@ -1014,20 +1016,41 @@ module GBA_ControlUnit (
 
             end else
 
-            // Latch the final fetched word into the register file and 
+            // Write the current register into memory and 
             // update the address bus back to PC for the next instruction
-            if (cycle == 8'd1 + 8'(regs_count)) begin
-
+            if (cycle == 8'(regs_count)) begin
               control_signals.Rp_imm =
                   get_ith_bit(4'(cycle - 8'd1), decoder_bus.word.arm.block.reg_list);
 
               control_signals.B_bus_source = B_BUS_SRC_REG_RP;
 
-              control_signals.addr_bus_src = ADDR_SRC_PC;
+              control_signals.addr_bus_src = ADDR_SRC_PC_RESTORE;
 
               // Write the next word in the block
               control_signals.memory_write_en = 1'b1;
 
+              $display("[ControlUnit] Cycle %0d of STM instruction, writing register R%0d to data",
+                       cycle, control_signals.Rp_imm);
+
+            end else
+
+            // We do not write this block. Instead we fetch the next instruction
+            // from memory and latch it to the fetched IR
+            if (cycle == 8'd1 + 8'(regs_count)) begin
+
+              control_signals |= fetch_next_instr();
+              // control_signals.incrementer_writeback = 1'b1;
+
+              control_signals.Rp_imm =
+                  get_ith_bit(4'(cycle - 8'd1), decoder_bus.word.arm.block.reg_list);
+
+              control_signals.B_bus_source = B_BUS_SRC_REG_RP;
+
+              control_signals.addr_bus_src = ADDR_SRC_INCR;
+
+              // We do not write the next word in the block
+              control_signals.memory_write_en = 1'b0;
+
               control_signals.pipeline_advance = 1'b1;
 
               $display(
diff --git a/cores/gba/rtl/cpu/control_types.sv b/cores/gba/rtl/cpu/control_types.sv
@@ -8,7 +8,7 @@ import gba_cpu_types_pkg::*;
 
 package gba_control_types_pkg;
 
-  typedef enum logic [1:0] {
+  typedef enum logic [2:0] {
     /// Don't change the current address on the address bus
     ADDR_SRC_NONE,
 
@@ -19,7 +19,11 @@ package gba_control_types_pkg;
     ADDR_SRC_ALU,
 
     /// Increments the current address on the address bus
-    ADDR_SRC_INCR
+    ADDR_SRC_INCR,
+
+    /// Places PC - 4 onto the address bus.
+    /// TODO maybe i can just remove ADDR_SRC_PC and make this the default?
+    ADDR_SRC_PC_RESTORE
   } address_source_t;
 
   typedef enum logic [1:0] {
@@ -218,8 +222,6 @@ package gba_control_types_pkg;
     // Pipeline Control
     // ======================================================
 
-    logic pipeline_flush;
-
     /// Control unit will handle the flush instead of the PC triggering one
     logic pipeline_handle_flush;
 
diff --git a/cores/gba/sim/include/gba.hpp b/cores/gba/sim/include/gba.hpp
@@ -64,6 +64,8 @@ class GameboyAdvanceHarness {
     /// Advances the simulation by one tick (clock).
     bool tick();
 
+    bool half_tick();
+
     /// Advance the simulation by one SM83 instruction.
     bool step();
 
diff --git a/cores/gba/sim/src/gba.cpp b/cores/gba/sim/src/gba.cpp
@@ -237,6 +237,15 @@ bool GameboyAdvanceHarness::began_instruction() const {
     }
 };
 
+bool GameboyAdvanceHarness::half_tick() {
+    top->clk = 0;
+    top->eval();
+    tfp->dump(ctx.time());
+    ctx.timeInc(5);
+
+    return true;
+}
+
 bool GameboyAdvanceHarness::tick() {
     top->clk = 0;
     top->eval();
diff --git a/cores/gba/tests/arm.gba/arm.surf.ron b/cores/gba/tests/arm.gba/arm.surf.ron
diff --git a/cores/gba/tests/arm.gba/test_arm.cpp b/cores/gba/tests/arm.gba/test_arm.cpp
