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work on BX
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4 files changed

+29
-8
lines changed

4 files changed

+29
-8
lines changed

cores/gba/rtl/cpu/CPU.sv

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -393,6 +393,13 @@ module ARM7TMDI (
393393
$display("Restoring CPSR from SPSR_%0d: 0x%08x", cpu_mode, read_spsr(regs, cpu_mode));
394394
end
395395

396+
if (control_signals.set_thumb_mode) begin
397+
regs.CPSR[5] <= B_bus[0];
398+
`WRITE_REG(regs, cpu_mode, 4'd15, B_bus & 32'hFFFFFFFE)
399+
flush_req <= 1'b1;
400+
$display("Setting Thumb mode bit in CPSR");
401+
end
402+
396403
if (control_signals.ALU_set_flags && control_signals.pipeline_advance) begin
397404

398405
if ((decoder_bus.word.Rd == 4'd15) && mode_has_spsr(
@@ -452,7 +459,6 @@ module ARM7TMDI (
452459
`WRITE_REG(regs, control_signals.force_user_mode ? CPU_MODE_USR : cpu_mode,
453460
decoder_bus.word.Rn, alu_bus.result)
454461
end
455-
ALU_WB_REG_14: `WRITE_REG(regs, cpu_mode, 14, alu_bus.result)
456462
ALU_WB_REG_RP: begin
457463
`WRITE_REG(regs, control_signals.force_user_mode ? CPU_MODE_USR : cpu_mode,
458464
control_signals.Rp_imm, alu_bus.result)

cores/gba/rtl/cpu/ControlUnit.sv

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1016,7 +1016,7 @@ module ControlUnit (
10161016
end
10171017

10181018
// ============================
1019-
// Branch & Branch with Link
1019+
// Branch
10201020
// ============================
10211021

10221022
ARM_INSTR_BRANCH: begin
@@ -1075,6 +1075,22 @@ module ControlUnit (
10751075
end
10761076
end
10771077

1078+
ARM_INSTR_BRANCH_EX: begin
1079+
if (cycle == 8'd0) begin
1080+
control_signals.ALU_op = ALU_OP_MOV;
1081+
control_signals.addr_bus_src = ADDR_SRC_ALU;
1082+
1083+
// control_signals.ALU_writeback = ALU_WB_REG_RP;
1084+
// control_signals.Rp_imm = 4'd15;
1085+
1086+
control_signals.B_bus_source = B_BUS_SRC_REG_RN;
1087+
1088+
control_signals.set_thumb_mode = 1'b1;
1089+
1090+
control_signals.pipeline_advance = 1'b1;
1091+
end
1092+
end
1093+
10781094
ARM_INSTR_SWI: begin
10791095
if (cycle == 8'd0) begin
10801096
// Rd should be R14 (LR)

cores/gba/rtl/cpu/Decoder.sv

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,8 @@ module GBA_Decoder (
4444
priority casez (IR)
4545
/// Branch and Branch Exchange
4646
32'b????_0001_0010_1111_1111_1111_0001_????: begin
47+
bus.word.instr_type = ARM_INSTR_BRANCH_EX;
48+
bus.word.Rn = IR[3:0];
4749
$display("[GBA_Decoder] Detected BX instruction with IR=0x%08x", IR);
4850
end
4951

cores/gba/rtl/cpu/control_types.sv

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -82,10 +82,7 @@ package gba_control_types_pkg;
8282
ALU_WB_REG_RN,
8383

8484
/// If set, we need also need to set `Rp_imm`
85-
ALU_WB_REG_RP,
86-
87-
/// Write back to register 14
88-
ALU_WB_REG_14
85+
ALU_WB_REG_RP
8986
} alu_writeback_source_t;
9087

9188
typedef struct packed {
@@ -114,6 +111,8 @@ package gba_control_types_pkg;
114111

115112
exception_t exception;
116113

114+
logic set_thumb_mode;
115+
117116
// ======================================================
118117
// A Bus
119118
// ======================================================
@@ -127,8 +126,6 @@ package gba_control_types_pkg;
127126
// B Bus
128127
// ======================================================
129128

130-
/// Hello
131-
/// There
132129
B_bus_source_t B_bus_source;
133130

134131
/// Immediate value to place on the B bus, if selected in `B_bus_source`

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