I am a PhD student from Northeastern University in Boston, US. I am considering using Coyote RDMA part in our project to communicate with Mellanox RDMA NIC. I am currently trying the static shell, but I am encountering the following errors.
** Starting shell compilation ...
**
Command: open_checkpoint /home/qianyich/Coyote/examples_hw/build_hw_ddr/checkpoints/shell_linked.dcp
Starting open_checkpoint Task
Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2724.719 ; gain = 5.938 ; free physical = 76417 ; free virtual = 90001
INFO: [Device 21-403] Loading part xcu280-fsvh2892-2L-e
Netlist sorting complete. Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 4748.578 ; gain = 77.000 ; free physical = 74409 ; free virtual = 87993
INFO: [Netlist 29-17] Analyzing 14880 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 3 CPU seconds
WARNING: [Netlist 29-1115] Found multi-term driver net: inst_static/inst_int_static/util_ds_buf/U0/<const0>.
INFO: [Project 1-479] Netlist was created with Vivado 2022.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'inst_shell/xclk' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'inst_static/inst_int_static/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Power 33-23] Power model is not available for xiphy_riu_or
INFO: [Power 33-23] Power model is not available for genVref.u_hpio_vref
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Constraints 18-4422] SNAPPING_MODE is set so implementation will use the DERIVED_RANGES which may be different then the GRID_RANGES.
INFO: [Constraints 18-4421] A LAGUNA range, without usable sites, was added to DERIVED_RANGES for purposes of keeping the Programmable Unit together within the reconfigurable pblock.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF Files: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.75 . Memory (MB): peak = 9436.719 ; gain = 0.000 ; free physical = 70266 ; free virtual = 83850
Restored from archive | CPU: 0.750000 secs | Memory: 4.954178 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.75 . Memory (MB): peak = 9436.719 ; gain = 0.000 ; free physical = 70266 ; free virtual = 83850
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2022.1/data/ip'.
Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 9436.719 ; gain = 0.000 ; free physical = 70374 ; free virtual = 83958
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 3321 instances were transformed.
CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 352 instances
DSP48E1 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 3 instances
IBUFDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance
IOBUFDS => IOBUFDS (DIFFINBUF, IBUFCTRL, INV, OBUFT(x2)): 18 instances
IOBUFE3 => IOBUFE3 (IBUFCTRL, INBUF, OBUFT_DCIEN): 72 instances
LUT6_2 => LUT6_2 (LUT5, LUT6): 31 instances
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUF(x2)): 1 instance
RAM16X1D => RAM32X1D (RAMD32(x2)): 7 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 9 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 336 instances
RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 2089 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 169 instances
RAM64M => RAM64M (RAMD64E(x4)): 9 instances
RAM64M8 => RAM64M8 (RAMD64E(x8)): 224 instances
INFO: [Project 1-604] Checkpoint was created with Vivado v2022.1 (64-bit) build 3526262
open_checkpoint: Time (s): cpu = 00:06:15 ; elapsed = 00:03:21 . Memory (MB): peak = 9436.719 ; gain = 6720.906 ; free physical = 70372 ; free virtual = 83957
Command: opt_design -directive Explore
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore
Attempting to get a license for feature 'Implementation' and/or device 'xcu280'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcu280'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors, 108 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:40 ; elapsed = 00:00:34 . Memory (MB): peak = 9514.406 ; gain = 77.688 ; free physical = 70170 ; free virtual = 83765
Starting Logic Optimization Task
Phase 1 Generate And Synthesize MIG Cores
ERROR: [Mig 66-99] Memory Core Error - [inst_shell/inst_int_ddr/ddr4_0] Either port(s) c0_sys_clk_p, c0_sys_clk_n is/are not placed or un-supported clocking structure/circuit for memory ip instance. Please refer to clocking section of PG150 for supported clocking structures.
ERROR: [Mig 66-99] Memory Core Error - [inst_shell/inst_int_ddr/ddr4_0] Port(s) c0_sys_clk_n,c0_sys_clk_p is/are not placed. Assign all ports to valid sites.
Phase 1 Generate And Synthesize MIG Cores | Checksum: 1ec633aea
Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.38 . Memory (MB): peak = 9514.406 ; gain = 0.000 ; free physical = 69960 ; free virtual = 83555
INFO: [Common 17-83] Releasing license: Implementation
25 Infos, 3 Warnings, 0 Critical Warnings and 3 Errors encountered.
opt_design failed
** CERR: ERROR: [Opt 31-306] MIG/Advanced IO Wizard Cores generation Failed.
**
INFO: [Common 17-206] Exiting Vivado at Fri Sep 20 12:11:50 2024...
I double-checked the ddr_0 constraints for u280 and I think it is all correct, but I have no idea why the tool throws this error.
Hi Coyote Maintainers:
I am a PhD student from Northeastern University in Boston, US. I am considering using Coyote RDMA part in our project to communicate with Mellanox RDMA NIC. I am currently trying the static shell, but I am encountering the following errors.
Vivado: 2022.1
Board: Alveo U280
Step to reproduce:
Error message when flow_comp.tcl is executed for shell compilation:
I double-checked the ddr_0 constraints for u280 and I think it is all correct, but I have no idea why the tool throws this error.