Issue#1503: Added new rules for array alignment within signal initialisations.

Author: JHertz5

vsg/rules/signal/__init__.py

@@ -22,4 +22,6 @@
 from .rule_200 import rule_200
 from .rule_400 import rule_400
 from .rule_401 import rule_401
+from .rule_402 import rule_402
+from .rule_403 import rule_403
 from .rule_600 import rule_600

vsg/rules/signal/rule_402.py

@@ -0,0 +1,44 @@
+# -*- coding: utf-8 -*-
+
+
+from vsg import token
+from vsg.rules import multiline_array_alignment as Rule
+
+lTokenPairs = []
+lTokenPairs.append([token.signal_declaration.assignment_operator, token.signal_declaration.semicolon])
+
+
+class rule_402(Rule):
+    """
+    This rule checks the alignment of multiline signal initializations that contain arrays.
+
+    |configuring_multiline_indent_rules_link|
+
+    .. NOTE:: The structure of multiline array signal initializations is handled by the rule `signal_403 <signal_rules.html#signal-403>`_.
+
+    **Violation**
+
+    .. code-block:: vhdl
+
+       signal rom : romq_type :=
+       (
+                0,
+            65535,
+            32768
+         );
+
+    **Fix**
+
+    .. code-block:: vhdl
+
+       signal rom : romq_type :=
+       (
+         0,
+         65535,
+         32768
+       );
+    """
+
+    def __init__(self):
+        super().__init__(lTokenPairs)
+        self.assignment_operator = token.signal_declaration.assignment_operator

vsg/rules/signal/rule_403.py

@@ -0,0 +1,40 @@
+# -*- coding: utf-8 -*-
+
+from vsg import token
+from vsg.rules import multiline_structure as Rule
+
+lTokenPairs = []
+lTokenPairs.append([token.signal_declaration.assignment_operator, token.signal_declaration.semicolon])
+
+
+class rule_403(Rule):
+    """
+    This rule checks the structure of multiline signal initializations that contain arrays.
+
+    |configuring_array_multiline_structure_rules_link|
+
+    .. NOTE:: The indenting of multiline array signal initializations is handled by the rule `signal_402 <signal_rules.html#signal-402>`_.
+
+    **Violation**
+
+    .. code-block:: vhdl
+
+       signal rom : romq_type := (0, 65535, 32768);
+
+    **Fix**
+
+    .. code-block:: vhdl
+
+       signal rom : romq_type :=
+       (
+         0,
+         65535,
+         32768
+       );
+    """
+
+    def __init__(self):
+        super().__init__(lTokenPairs)
+        self.assignment_operator = token.signal_declaration.assignment_operator
+        self.semicolon = token.signal_declaration.semicolon
+        self.phase = 5