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Merge pull request #1493 from JHertz5/issue-1490
Issue#1490: Added whitespace rules for direction keywords
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‎docs/configuring_whitespace_rules.rst‎

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@@ -288,3 +288,5 @@ Rules Enforcing Whitespace
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* `variable_assignment_002 <variable_assignment_rules.html#variable-assignment-002>`_
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* `variable_assignment_003 <variable_assignment_rules.html#variable-assignment-003>`_
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* `whitespace_007 <whitespace_rules.html#whitespace-007>`_
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* `whitespace_102 <whitespace_rules.html#whitespace-102>`_
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* `whitespace_103 <whitespace_rules.html#whitespace-103>`_

‎docs/rule_groups/whitespace_rule_group.rst‎

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* `whitespace_013 <../whitespace_rules.html#whitespace-013>`_
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* `whitespace_100 <../whitespace_rules.html#whitespace-100>`_
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* `whitespace_101 <../whitespace_rules.html#whitespace-101>`_
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* `whitespace_102 <../whitespace_rules.html#whitespace-102>`_
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* `whitespace_103 <../whitespace_rules.html#whitespace-103>`_

‎docs/whitespace_rules.rst‎

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@@ -290,6 +290,52 @@ This rule checks for at least a single space before and after logical operators.
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if (a = '1') sll (b = '0')
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if (a = '0') rol (b = '1')
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whitespace_102
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##############
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|phase_2| |error| |whitespace|
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This rule checks for a single space before direction keywords.
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|configuring_whitespace_rules_link|
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**Violation**
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.. code-block:: vhdl
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x <= y(7 downto 0);
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x <= y(0 to 7);
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**Fix**
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.. code-block:: vhdl
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x <= y(7 downto 0);
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x <= y(0 to 7);
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whitespace_103
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##############
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|phase_2| |error| |whitespace|
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This rule checks for a single space after direction keywords.
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|configuring_whitespace_rules_link|
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**Violation**
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.. code-block:: vhdl
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x <= y(7 downto 0);
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x <= y(0 to 7);
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**Fix**
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.. code-block:: vhdl
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x <= y(7 downto 0);
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x <= y(0 to 7);
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whitespace_200
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##############
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‎tests/whitespace/rule_102_test_input.fixed.vhd‎

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entity b is
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port (
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c : in std_logic_vector(7 downto 0)
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);
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end entity b;
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architecture a of b is
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type my_array2 is array (natural range 0 to 7) of std_logic_vector(7 downto 0);
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subtype my_array3 is my_array2(open)(7 downto 0);
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subtype my_array4 is natural range 0 to 7;
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begin
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x <= y(7 downto 0);
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end architecture a;

‎tests/whitespace/rule_102_test_input.vhd‎

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entity b is
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port (
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c : in std_logic_vector(7 downto 0)
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);
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end entity b;
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architecture a of b is
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type my_array2 is array (natural range 0 to 7) of std_logic_vector(7 downto 0);
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subtype my_array3 is my_array2(open)(7 downto 0);
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subtype my_array4 is natural range 0 to 7;
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begin
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x <= y(7 downto 0);
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end architecture a;

‎tests/whitespace/rule_103_test_input.fixed.vhd‎

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entity b is
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port (
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c : in std_logic_vector(7 downto 0)
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);
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end entity b;
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architecture a of b is
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type my_array2 is array (natural range 0 to 7) of std_logic_vector(7 downto 0);
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subtype my_array3 is my_array2(open)(7 downto 0);
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subtype my_array4 is natural range 0 to 7;
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begin
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x <= y(7 downto 0);
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end architecture a;

‎tests/whitespace/rule_103_test_input.vhd‎

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entity b is
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port (
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c : in std_logic_vector(7 downto 0)
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);
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end entity b;
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architecture a of b is
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type my_array2 is array (natural range 0 to 7) of std_logic_vector(7 downto 0);
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subtype my_array3 is my_array2(open)(7 downto 0);
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subtype my_array4 is natural range 0 to 7;
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begin
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x <= y(7 downto 0);
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end architecture a;

‎tests/whitespace/test_rule_102.py‎

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# -*- coding: utf-8 -*-
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import os
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import unittest
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from tests import utils
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from vsg import vhdlFile
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from vsg.rules import whitespace
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sTestDir = os.path.dirname(__file__)
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lFile, eError = vhdlFile.utils.read_vhdlfile(os.path.join(sTestDir, "rule_102_test_input.vhd"))
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lExpected = []
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lExpected.append("")
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utils.read_file(os.path.join(sTestDir, "rule_102_test_input.fixed.vhd"), lExpected)
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class test_rule(unittest.TestCase):
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def setUp(self):
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self.oFile = vhdlFile.vhdlFile(lFile)
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self.assertIsNone(eError)
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def test_rule_102(self):
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oRule = whitespace.rule_102()
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self.assertTrue(oRule)
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self.assertEqual(oRule.name, "whitespace")
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self.assertEqual(oRule.identifier, "102")
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lExpected = [4, 10, 10, 12, 14, 18]
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oRule.analyze(self.oFile)
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self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
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def test_fix_rule_102(self):
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oRule = whitespace.rule_102()
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oRule.fix(self.oFile)
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lActual = self.oFile.get_lines()
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self.assertEqual(lExpected, lActual)
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oRule.analyze(self.oFile)
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self.assertEqual(oRule.violations, [])

‎tests/whitespace/test_rule_103.py‎

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# -*- coding: utf-8 -*-
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import os
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import unittest
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from tests import utils
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from vsg import vhdlFile
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from vsg.rules import whitespace
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sTestDir = os.path.dirname(__file__)
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lFile, eError = vhdlFile.utils.read_vhdlfile(os.path.join(sTestDir, "rule_103_test_input.vhd"))
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lExpected = []
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lExpected.append("")
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utils.read_file(os.path.join(sTestDir, "rule_103_test_input.fixed.vhd"), lExpected)
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class test_rule(unittest.TestCase):
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def setUp(self):
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self.oFile = vhdlFile.vhdlFile(lFile)
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self.assertIsNone(eError)
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def test_rule_103(self):
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oRule = whitespace.rule_103()
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self.assertTrue(oRule)
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self.assertEqual(oRule.name, "whitespace")
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self.assertEqual(oRule.identifier, "103")
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lExpected = [4, 10, 10, 12, 14, 18]
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oRule.analyze(self.oFile)
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self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
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def test_fix_rule_103(self):
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oRule = whitespace.rule_103()
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oRule.fix(self.oFile)
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lActual = self.oFile.get_lines()
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self.assertEqual(lExpected, lActual)
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oRule.analyze(self.oFile)
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self.assertEqual(oRule.violations, [])

‎vsg/rules/whitespace/__init__.py‎

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from .rule_013 import rule_013
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from .rule_100 import rule_100
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from .rule_101 import rule_101
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from .rule_102 import rule_102
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from .rule_103 import rule_103
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from .rule_200 import rule_200

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