Issue#1511: Added tests for new rule to enforce position of assignment operator in variable declarations.

Author: JHertz5

tests/variable/rule_018_test_input.fixed.vhd

@@ -0,0 +1,45 @@
+
+architecture RTL of FIFO is
+
+begin
+
+  my_proc : process
+
+    variable c_width : integer;
+
+    variable c_width : integer := 16;
+
+    variable c_depth : integer :=
+     512;
+
+    variable AVMM_MASTER_NULL  : avmm_master_t := (
+      (others => '0'),
+      (others => '0'),
+      '0',
+      '0'
+    );
+
+    --! Test stimulus
+      CONSTANT c_stimulus : t_stimulus_array :=
+      (
+          (
+              name      => "Hold in reset       ",
+              clk_in    => "0101010101010101",
+              rst_in    => "1111111111111111",
+              cnt_en_in => "0000000000000000",
+              cnt_out   => "0000000000000000"
+          ),
+          (
+              name      => "Not enabled         ",
+              clk_in    => "0101010101010101",
+              rst_in    => "0000000000000000",
+              cnt_en_in => "0000000000000000",
+              cnt_out   => "0000000000000000"
+          )
+    );
+
+  begin
+
+  end process;
+
+end architecture RTL;

tests/variable/rule_018_test_input.vhd

@@ -0,0 +1,45 @@
+
+architecture RTL of FIFO is
+
+begin
+
+  my_proc : process
+
+    variable c_width : integer;
+
+    variable c_width : integer := 16;
+
+    variable c_depth : integer
+    := 512;
+
+    variable AVMM_MASTER_NULL  : avmm_master_t := (
+      (others => '0'),
+      (others => '0'),
+      '0',
+      '0'
+    );
+
+    --! Test stimulus
+      CONSTANT c_stimulus : t_stimulus_array :=
+      (
+          (
+              name      => "Hold in reset       ",
+              clk_in    => "0101010101010101",
+              rst_in    => "1111111111111111",
+              cnt_en_in => "0000000000000000",
+              cnt_out   => "0000000000000000"
+          ),
+          (
+              name      => "Not enabled         ",
+              clk_in    => "0101010101010101",
+              rst_in    => "0000000000000000",
+              cnt_en_in => "0000000000000000",
+              cnt_out   => "0000000000000000"
+          )
+    );
+
+  begin
+
+  end process;
+
+end architecture RTL;

tests/variable/test_rule_018.py

@@ -0,0 +1,46 @@
+# -*- coding: utf-8 -*-
+
+import os
+import unittest
+
+from tests import utils
+from vsg import vhdlFile
+from vsg.rules import variable
+
+sTestDir = os.path.dirname(__file__)
+
+lFile, eError = vhdlFile.utils.read_vhdlfile(os.path.join(sTestDir, "rule_018_test_input.vhd"))
+
+lExpected = []
+lExpected.append("")
+utils.read_file(os.path.join(sTestDir, "rule_018_test_input.fixed.vhd"), lExpected)
+
+
+class test_rule(unittest.TestCase):
+    def setUp(self):
+        self.oFile = vhdlFile.vhdlFile(lFile)
+        self.assertIsNone(eError)
+
+    def test_rule_018(self):
+        oRule = variable.rule_018()
+        self.assertTrue(oRule)
+        self.assertEqual(oRule.name, "variable")
+        self.assertEqual(oRule.identifier, "018")
+        self.assertEqual(oRule.groups, ["structure"])
+
+        lExpected = [12]
+
+        oRule.analyze(self.oFile)
+        self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
+
+    def test_fix_rule_018(self):
+        oRule = variable.rule_018()
+
+        oRule.fix(self.oFile)
+
+        lActual = self.oFile.get_lines()
+
+        self.assertEqual(lExpected, lActual)
+
+        oRule.analyze(self.oFile)
+        self.assertEqual(oRule.violations, [])