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Merge remote-tracking branch 'origin/master' into issue-1492
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docs/array_constraint_rules.rst

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Array Constraint Rules
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----------------------
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array_constraint_100
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####################
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|phase_2| |error| |whitespace|
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This rule checks for whitespace before the opening parenthesis.
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|configuring_whitespace_rules_link|
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**Violation**
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.. code-block:: vhdl
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subtype my_array3 is my_array2 (open)(7 downto 0);
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**Fix**
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.. code-block:: vhdl
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subtype my_array3 is my_array2(open)(7 downto 0);
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array_constraint_500
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####################
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docs/configuring_whitespace_rules.rst

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* `architecture_031 <architecture_rules.html#architecture-031>`_
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* `architecture_032 <architecture_rules.html#architecture-032>`_
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* `architecture_033 <architecture_rules.html#architecture-033>`_
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* `array_constraint_100 <array_constraint_rules.html#array-constraint-100>`_
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* `assert_100 <assert_rules.html#assert-100>`_
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* `assert_101 <assert_rules.html#assert-101>`_
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* `assert_102 <assert_rules.html#assert-102>`_
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* `if_004 <if_rules.html#if-004>`_
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* `if_005 <if_rules.html#if-005>`_
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* `if_015 <if_rules.html#if-015>`_
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* `index_constraint_100 <index_constraint_rules.html#index-constraint-100>`_
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* `index_subtype_definition_100 <index_subtype_definition_rules.html#index-subtype-definition-100>`_
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* `index_subtype_definition_101 <index_subtype_definition_rules.html#index-subtype-definition-101>`_
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* `instantiation_002 <instantiation_rules.html#instantiation-002>`_

docs/index_constraint_rules.rst

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.. include:: includes.rst
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Index Constraint Rules
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----------------------
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index_constraint_100
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####################
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|phase_2| |error| |whitespace|
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This rule checks for whitespace before the opening parenthesis.
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|configuring_whitespace_rules_link|
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**Violation**
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.. code-block:: vhdl
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subtype my_array3 is my_array2(open) (7 downto 0);
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**Fix**
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.. code-block:: vhdl
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subtype my_array3 is my_array2(open)(7 downto 0);

docs/rule_groups/whitespace_rule_group.rst

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* `architecture_031 <../architecture_rules.html#architecture-031>`_
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* `architecture_032 <../architecture_rules.html#architecture-032>`_
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* `architecture_033 <../architecture_rules.html#architecture-033>`_
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* `array_constraint_100 <../array_constraint_rules.html#array-constraint-100>`_
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* `assert_100 <../assert_rules.html#assert-100>`_
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* `assert_101 <../assert_rules.html#assert-101>`_
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* `assert_102 <../assert_rules.html#assert-102>`_
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* `if_004 <../if_rules.html#if-004>`_
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* `if_005 <../if_rules.html#if-005>`_
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* `if_015 <../if_rules.html#if-015>`_
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* `index_constraint_100 <../index_constraint_rules.html#index-constraint-100>`_
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* `index_subtype_definition_100 <../index_subtype_definition_rules.html#index-subtype-definition-100>`_
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* `index_subtype_definition_101 <../index_subtype_definition_rules.html#index-subtype-definition-101>`_
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* `instantiation_002 <../instantiation_rules.html#instantiation-002>`_
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* `whitespace_005 <../whitespace_rules.html#whitespace-005>`_
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* `whitespace_006 <../whitespace_rules.html#whitespace-006>`_
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* `whitespace_007 <../whitespace_rules.html#whitespace-007>`_
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* `whitespace_008 <../whitespace_rules.html#whitespace-008>`_
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* `whitespace_010 <../whitespace_rules.html#whitespace-010>`_
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* `whitespace_011 <../whitespace_rules.html#whitespace-011>`_
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* `whitespace_013 <../whitespace_rules.html#whitespace-013>`_

docs/whitespace_rules.rst

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whitespace_008
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##############
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|phase_2| |error| |whitespace|
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This rule checks for spaces after the **std_logic_vector** keyword.
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**Violation**
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.. code-block:: vhdl
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signal data : std_logic_vector (7 downto 0);
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signal counter : std_logic_vector (7 downto 0);
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**Fix**
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.. code-block:: vhdl
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signal data : std_logic_vector(7 downto 0);
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signal counter : std_logic_vector(7 downto 0);
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This rule has been deprecated and replaced with rule `index_constraint_100 <index_constraint_rules.html#index_constraint-100>`_.
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whitespace_010
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##############
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architecture rtl of fifo is
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subtype t_my_array is t_array(open)(t_range);
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subtype t_my_array is t_array(open)(t_range);
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subtype t_my_array is t_array(open)(t_range);
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begin
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end architecture rtl;
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architecture rtl of fifo is
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subtype t_my_array is t_array (open)(t_range);
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subtype t_my_array is t_array (open)(t_range);
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subtype t_my_array is t_array(open)(t_range);
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begin
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end architecture rtl;
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# -*- coding: utf-8 -*-
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import os
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import unittest
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from tests import utils
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from vsg import vhdlFile
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from vsg.rules import array_constraint
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sTestDir = os.path.dirname(__file__)
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lFile, eError = vhdlFile.utils.read_vhdlfile(os.path.join(sTestDir, "rule_100_test_input.vhd"))
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lExpected = []
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lExpected.append("")
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utils.read_file(os.path.join(sTestDir, "rule_100_test_input.fixed.vhd"), lExpected)
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class test_rule(unittest.TestCase):
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def setUp(self):
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self.oFile = vhdlFile.vhdlFile(lFile)
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self.assertIsNone(eError)
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def test_rule_100(self):
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oRule = array_constraint.rule_100()
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self.assertTrue(oRule)
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self.assertEqual(oRule.name, "array_constraint")
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self.assertEqual(oRule.identifier, "100")
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lExpected = [4, 5]
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oRule.analyze(self.oFile)
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self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
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def test_fix_rule_100(self):
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oRule = array_constraint.rule_100()
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oRule.fix(self.oFile)
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lActual = self.oFile.get_lines()
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self.assertEqual(lExpected, lActual)
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oRule.analyze(self.oFile)
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self.assertEqual(oRule.violations, [])

tests/index_constraint/__init__.py

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entity fifo is
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port (
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i_data : in signed(15 downto 0);
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i_data : in signed(15 downto 0);
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i_data : in signed(15 downto 0)
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);
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end entity fifo;
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architecture rtl of fifo is
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subtype t_my_array is t_array(open)(t_range);
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subtype t_my_array is t_array(open)(t_range);
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subtype t_my_array is t_array(open)(t_range);
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begin
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end architecture rtl;

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