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Issue#1250: Corrected alignment of multiline variable and signal declarations for align_left = no (#1345)
* Issue#1250: Corrections to multiline_alignment for method _analyze_align_left_no_align_paren_yes. * Issue#1250: Updated tests after corrections to multiline_alignment for method _analyze_align_left_no_align_paren_yes. * Issue#1250: Updates after merge of issue-1290. * Issue#1250: Updated "align_left no, align_paren no" alignment as well. * Issue#1250: Updated tests for signal_400. * Issue#1250: Updated tests for variable_400. * Issue#1250: Formatting.
1 parent 285768d commit e02087d

13 files changed

+212
-81
lines changed

‎tests/signal/rule_400_test_input.fixed__align_left_no__align_paren_no.vhd‎

Lines changed: 28 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,29 +1,39 @@
11
architecture rtl of fifo is
22

33
signal sig8 : record_type_3(
4-
element1(7 downto 0),
5-
element2(4 downto 0)(7 downto 0)
6-
(
7-
elementA(7 downto 0),
8-
elementB(3 downto 0)
9-
),
10-
element3(3 downto 0)(
11-
elementC(4 downto 1),
12-
elementD(1 downto 0)),
13-
element5(
14-
elementE(3 downto 0)(6 downto 0),
15-
elementF(7 downto 0)
16-
),
17-
element6(4 downto 0),
18-
element7(7 downto 0)
4+
element1(7 downto 0),
5+
element2(4 downto 0)(7 downto 0)
6+
(
7+
elementA(7 downto 0),
8+
elementB(3 downto 0)
9+
),
10+
element3(3 downto 0)(
11+
elementC(4 downto 1),
12+
elementD(1 downto 0)),
13+
element5(
14+
elementE(3 downto 0)(6 downto 0),
15+
elementF(7 downto 0)
16+
),
17+
element6(4 downto 0),
18+
element7(7 downto 0)
1919
);
2020

2121
signal s : MY_TYPE := (
22-
a => '0',
23-
ddddd => (others => '0'),
24-
ffff => (others => '0')
22+
a => '0',
23+
ddddd => (others => '0'),
24+
ffff => (others => '0')
2525
);
2626

27+
signal AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
28+
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
29+
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
30+
w_data(DataRange_c),
31+
w_strb(ByteRange_c));
32+
33+
signal AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
34+
r_user(UserRange_c), b_user(UserRange_c),
35+
r_data(DataRange_c));
36+
2737
begin
2838

2939
end architecture rtl;

‎tests/signal/rule_400_test_input.fixed__align_left_no__align_paren_yes.vhd‎

Lines changed: 28 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,29 +1,39 @@
11
architecture rtl of fifo is
22

33
signal sig8 : record_type_3(
4-
element1(7 downto 0),
5-
element2(4 downto 0)(7 downto 0)
6-
(
7-
elementA(7 downto 0),
8-
elementB(3 downto 0)
9-
),
10-
element3(3 downto 0)(
11-
elementC(4 downto 1),
12-
elementD(1 downto 0)),
13-
element5(
14-
elementE(3 downto 0)(6 downto 0),
15-
elementF(7 downto 0)
16-
),
17-
element6(4 downto 0),
18-
element7(7 downto 0)
4+
element1(7 downto 0),
5+
element2(4 downto 0)(7 downto 0)
6+
(
7+
elementA(7 downto 0),
8+
elementB(3 downto 0)
9+
),
10+
element3(3 downto 0)(
11+
elementC(4 downto 1),
12+
elementD(1 downto 0)),
13+
element5(
14+
elementE(3 downto 0)(6 downto 0),
15+
elementF(7 downto 0)
16+
),
17+
element6(4 downto 0),
18+
element7(7 downto 0)
1919
);
2020

2121
signal s : MY_TYPE := (
22-
a => '0',
23-
ddddd => (others => '0'),
24-
ffff => (others => '0')
22+
a => '0',
23+
ddddd => (others => '0'),
24+
ffff => (others => '0')
2525
);
2626

27+
signal AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
28+
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
29+
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
30+
w_data(DataRange_c),
31+
w_strb(ByteRange_c));
32+
33+
signal AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
34+
r_user(UserRange_c), b_user(UserRange_c),
35+
r_data(DataRange_c));
36+
2737
begin
2838

2939
end architecture rtl;

‎tests/signal/rule_400_test_input.fixed__align_left_yes__align_paren_no.vhd‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,16 @@ architecture rtl of fifo is
2424
ffff => (others => '0')
2525
);
2626

27+
signal AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
28+
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
29+
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
30+
w_data(DataRange_c),
31+
w_strb(ByteRange_c));
32+
33+
signal AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
34+
r_user(UserRange_c), b_user(UserRange_c),
35+
r_data(DataRange_c));
36+
2737
begin
2838

2939
end architecture rtl;

‎tests/signal/rule_400_test_input.fixed__align_left_yes__align_paren_yes.vhd‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,16 @@ architecture rtl of fifo is
2424
ffff => (others => '0')
2525
);
2626

27+
signal AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
28+
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
29+
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
30+
w_data(DataRange_c),
31+
w_strb(ByteRange_c));
32+
33+
signal AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
34+
r_user(UserRange_c), b_user(UserRange_c),
35+
r_data(DataRange_c));
36+
2737
begin
2838

2939
end architecture rtl;

‎tests/signal/rule_400_test_input.vhd‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,16 @@ elementE(3 downto 0)(6 downto 0),
2424
ffff => (others => '0')
2525
);
2626

27+
signal AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
28+
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
29+
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
30+
w_data(DataRange_c),
31+
w_strb(ByteRange_c));
32+
33+
signal AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
34+
r_user(UserRange_c), b_user(UserRange_c),
35+
r_data(DataRange_c));
36+
2737
begin
2838

2939
end architecture rtl;

‎tests/signal/test_rule_400.py‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,8 @@ def test_rule_400__align_left_yes__align_paren_no(self):
4949
lExpected = []
5050
lExpected.extend(range(5, 20))
5151
lExpected.extend(range(22, 26))
52+
lExpected.extend(range(28, 32))
53+
lExpected.extend(range(34, 36))
5254

5355
oRule.analyze(self.oFile)
5456
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
@@ -65,6 +67,8 @@ def test_rule_400__align_left_true__align_paren_false(self):
6567
lExpected = []
6668
lExpected.extend(range(5, 20))
6769
lExpected.extend(range(22, 26))
70+
lExpected.extend(range(28, 32))
71+
lExpected.extend(range(34, 36))
6872

6973
oRule.analyze(self.oFile)
7074
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
@@ -95,6 +99,8 @@ def test_rule_400__align_left_no__align_paren_no(self):
9599
lExpected = []
96100
lExpected.extend(range(4, 20))
97101
lExpected.extend(range(22, 26))
102+
lExpected.extend(range(28, 32))
103+
lExpected.extend(range(34, 36))
98104

99105
oRule.analyze(self.oFile)
100106
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
@@ -111,6 +117,8 @@ def test_rule_400__align_left_false__align_paren_false(self):
111117
lExpected = []
112118
lExpected.extend(range(4, 20))
113119
lExpected.extend(range(22, 26))
120+
lExpected.extend(range(28, 32))
121+
lExpected.extend(range(34, 36))
114122

115123
oRule.analyze(self.oFile)
116124
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
@@ -141,6 +149,8 @@ def test_rule_400__align_left_no__align_paren_yes(self):
141149
lExpected = []
142150
lExpected.extend(range(4, 20))
143151
lExpected.extend(range(22, 26))
152+
lExpected.extend(range(28, 32))
153+
lExpected.extend(range(34, 36))
144154

145155
oRule.analyze(self.oFile)
146156
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
@@ -157,6 +167,8 @@ def test_rule_400__align_left_false__align_paren_true(self):
157167
lExpected = []
158168
lExpected.extend(range(4, 20))
159169
lExpected.extend(range(22, 26))
170+
lExpected.extend(range(28, 32))
171+
lExpected.extend(range(34, 36))
160172

161173
oRule.analyze(self.oFile)
162174
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
@@ -187,6 +199,8 @@ def test_rule_400__align_left_yes__align_paren_yes(self):
187199
lExpected = []
188200
lExpected.extend(range(5, 20))
189201
lExpected.extend(range(22, 26))
202+
lExpected.extend(range(28, 32))
203+
lExpected.extend(range(34, 36))
190204

191205
oRule.analyze(self.oFile)
192206
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
@@ -203,6 +217,8 @@ def test_rule_400__align_left_true__align_paren_true(self):
203217
lExpected = []
204218
lExpected.extend(range(5, 20))
205219
lExpected.extend(range(22, 26))
220+
lExpected.extend(range(28, 32))
221+
lExpected.extend(range(34, 36))
206222

207223
oRule.analyze(self.oFile)
208224
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))

‎tests/variable/rule_400_test_input.fixed__align_left_no__align_paren_no.vhd‎

Lines changed: 28 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,29 +1,39 @@
11
architecture rtl of fifo is
22

33
variable v_element : record_type_3(
4-
element1(7 downto 0),
5-
element2(4 downto 0)(7 downto 0)
6-
(
7-
elementA(7 downto 0),
8-
elementB(3 downto 0)
9-
),
10-
element3(3 downto 0)(
11-
elementC(4 downto 1),
12-
elementD(1 downto 0)),
13-
element5(
14-
elementE(3 downto 0)(6 downto 0),
15-
elementF(7 downto 0)
16-
),
17-
element6(4 downto 0),
18-
element7(7 downto 0)
4+
element1(7 downto 0),
5+
element2(4 downto 0)(7 downto 0)
6+
(
7+
elementA(7 downto 0),
8+
elementB(3 downto 0)
9+
),
10+
element3(3 downto 0)(
11+
elementC(4 downto 1),
12+
elementD(1 downto 0)),
13+
element5(
14+
elementE(3 downto 0)(6 downto 0),
15+
elementF(7 downto 0)
16+
),
17+
element6(4 downto 0),
18+
element7(7 downto 0)
1919
);
2020

2121
variable v : MY_TYPE := (
22-
a => '0',
23-
ddddd => (others => '0'),
24-
ffff => (others => '0')
22+
a => '0',
23+
ddddd => (others => '0'),
24+
ffff => (others => '0')
2525
);
2626

27+
variable AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
28+
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
29+
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
30+
w_data(DataRange_c),
31+
w_strb(ByteRange_c));
32+
33+
variable AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
34+
r_user(UserRange_c), b_user(UserRange_c),
35+
r_data(DataRange_c));
36+
2737
begin
2838

2939
end architecture rtl;

‎tests/variable/rule_400_test_input.fixed__align_left_no__align_paren_yes.vhd‎

Lines changed: 28 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,29 +1,39 @@
11
architecture rtl of fifo is
22

33
variable v_element : record_type_3(
4-
element1(7 downto 0),
5-
element2(4 downto 0)(7 downto 0)
6-
(
7-
elementA(7 downto 0),
8-
elementB(3 downto 0)
9-
),
10-
element3(3 downto 0)(
11-
elementC(4 downto 1),
12-
elementD(1 downto 0)),
13-
element5(
14-
elementE(3 downto 0)(6 downto 0),
15-
elementF(7 downto 0)
16-
),
17-
element6(4 downto 0),
18-
element7(7 downto 0)
4+
element1(7 downto 0),
5+
element2(4 downto 0)(7 downto 0)
6+
(
7+
elementA(7 downto 0),
8+
elementB(3 downto 0)
9+
),
10+
element3(3 downto 0)(
11+
elementC(4 downto 1),
12+
elementD(1 downto 0)),
13+
element5(
14+
elementE(3 downto 0)(6 downto 0),
15+
elementF(7 downto 0)
16+
),
17+
element6(4 downto 0),
18+
element7(7 downto 0)
1919
);
2020

2121
variable v : MY_TYPE := (
22-
a => '0',
23-
ddddd => (others => '0'),
24-
ffff => (others => '0')
22+
a => '0',
23+
ddddd => (others => '0'),
24+
ffff => (others => '0')
2525
);
2626

27+
variable AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
28+
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
29+
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
30+
w_data(DataRange_c),
31+
w_strb(ByteRange_c));
32+
33+
variable AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
34+
r_user(UserRange_c), b_user(UserRange_c),
35+
r_data(DataRange_c));
36+
2737
begin
2838

2939
end architecture rtl;

‎tests/variable/rule_400_test_input.fixed__align_left_yes__align_paren_no.vhd‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,16 @@ architecture rtl of fifo is
2424
ffff => (others => '0')
2525
);
2626

27+
variable AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
28+
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
29+
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
30+
w_data(DataRange_c),
31+
w_strb(ByteRange_c));
32+
33+
variable AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
34+
r_user(UserRange_c), b_user(UserRange_c),
35+
r_data(DataRange_c));
36+
2737
begin
2838

2939
end architecture rtl;

‎tests/variable/rule_400_test_input.fixed__align_left_yes__align_paren_yes.vhd‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,16 @@ architecture rtl of fifo is
2424
ffff => (others => '0')
2525
);
2626

27+
variable AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
28+
ar_addr(AddrRange_c), aw_addr(AddrRange_c),
29+
ar_user(UserRange_c), aw_user(UserRange_c), w_user(UserRange_c),
30+
w_data(DataRange_c),
31+
w_strb(ByteRange_c));
32+
33+
variable AxiSm : axi_sm_t (r_id(IdRange_c), b_id(IdRange_c),
34+
r_user(UserRange_c), b_user(UserRange_c),
35+
r_data(DataRange_c));
36+
2737
begin
2838

2939
end architecture rtl;

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