Is your feature request related to a problem? Please describe.
I would like to have whitespace rules for case generates, equivalent to those for case statements. At the moment, when I run the following code
architecture rtl of test is
begin
gen_label : case my_expression generate
when OPTION_1 =>
sig1 <= sig2;
end generate gen_label;
proc_label : process (all) is
begin
case my_expression is
when OPTION_1 =>
sig1 <= sig2;
end case;
end process proc_label;
end architecture rtl;I only get errors for the case statement
$ bin/vsg -f test.vhd
================================================================================
File: test.vhd
================================================================================
Phase 3 of 7... Reporting
Total Rules Checked: 441
Total Violations: 3
Error : 3
Warning : 0
-----------+------------+------------+--------------------------------------
Rule | severity | line(s) | Solution
-----------+------------+------------+--------------------------------------
case_200 | Error | 14 | Insert blank line below
case_201 | Error | 14 | Insert blank line above
case_009 | Error | 16 | Insert blank line above
-----------+------------+------------+--------------------------------------
NOTE: Refer to online documentation at https://vhdl-style-guide.readthedocs.io/en/latest/index.html for more information.
Describe the solution you'd like
I would like rules to correct the code above to
architecture rtl of test is
begin
gen_label : case my_expression generate
when OPTION_1 =>
sig1 <= sig2;
end generate gen_label;
proc_label : process (all) is
begin
case my_expression is
when OPTION_1 =>
sig1 <= sig2;
end case;
end process proc_label;
end architecture rtl;rather than
architecture rtl of test is
begin
gen_label : case my_expression generate
when OPTION_1 =>
sig1 <= sig2;
end generate gen_label;
proc_label : process (all) is
begin
case my_expression is
when OPTION_1 =>
sig1 <= sig2;
end case;
end process proc_label;
end architecture rtl;
Is your feature request related to a problem? Please describe.
I would like to have whitespace rules for case generates, equivalent to those for case statements. At the moment, when I run the following code
I only get errors for the case statement
Describe the solution you'd like
I would like rules to correct the code above to
rather than