Environment
VSG 3.30

Describe the bug
Error when accessing record elements of a vhdl-2008 referenced record.
ALIAS alias_sop: std_logic IS << signal .tb_top.submodule.i_rx_data : t_mac_interface >> .sop;
t_mac_interface is a record with an sop element that is a std_logic
Code is valid (at least according to Modelsim :D)

To Reproduce
Simply Execute vsg on a file with mentioned code

Expected behavior
No Error :)

Additional context
Generally Thank You for working on VSG, we adapted our code formating about a year ago and it's working really well so far :)