Add support for VHDL 2019 trailing semicolon

[linknum23]

VHDL 2019 added an extra optional semicolon to interface lists. This means that you can add an optional semicolon to port/generic interface lists in entity declarations as well as parameter lists in procedure and function definitions.

entity someEntity is
port (
  a : std_logic;
  b : integer;
);
end entity; 

When this is added we should add a rule to enable/disable/no-change it, with disabled being the default. If a VHDL-2019 group ever gets added, the default for that may be either enable or no-change.