diff --git a/docs/configuring_blank_lines.rst b/docs/configuring_blank_lines.rst index f052e7904..f1b0e83ba 100644 --- a/docs/configuring_blank_lines.rst +++ b/docs/configuring_blank_lines.rst @@ -157,6 +157,7 @@ Rules Enforcing Blank Lines * `entity_202 `_ * `entity_203 `_ * `generate_003 `_ +* `generic_map_201 `_ * `if_030 `_ * `instantiation_019 `_ * `loop_statement_201 `_ @@ -169,6 +170,7 @@ Rules Enforcing Blank Lines * `package_instantiation_201 `_ * `port_001 `_ * `port_map_200 `_ +* `port_map_201 `_ * `pragma_401 `_ * `pragma_403 `_ * `process_011 `_ diff --git a/docs/generic_map_rules.rst b/docs/generic_map_rules.rst index c7a1c4f7e..4d3cedfd3 100644 --- a/docs/generic_map_rules.rst +++ b/docs/generic_map_rules.rst @@ -292,6 +292,46 @@ This rule checks for a single space between the **generic** keyword and the **ma generic map ( +generic_map_201 +############### + +|phase_3| |error| |blank_line| + +This rule checks for blank lines in a generic map. + +|configuring_blank_lines_link| + +**Violation** + +.. code-block:: vhdl + + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + +**Fix** + +.. code-block:: vhdl + + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + generic_map_300 ############### diff --git a/docs/port_map_rules.rst b/docs/port_map_rules.rst index ce9ad01e3..c9fc82ff8 100644 --- a/docs/port_map_rules.rst +++ b/docs/port_map_rules.rst @@ -383,6 +383,47 @@ This rule checks for a blank line below the open parenthesis in a port map. OVERFLOW => w_overflow ); +port_map_201 +############ + +|phase_3| |error| |blank_line| + +This rule checks for blank lines in a port map. + +|configuring_blank_lines_link| + +**Violation** + +.. code-block:: vhdl + + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + +**Fix** + +.. code-block:: vhdl + + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + port_map_300 ############ diff --git a/docs/rule_groups/blank_line_rule_group.rst b/docs/rule_groups/blank_line_rule_group.rst index 143d181e6..75502dd6c 100644 --- a/docs/rule_groups/blank_line_rule_group.rst +++ b/docs/rule_groups/blank_line_rule_group.rst @@ -41,6 +41,7 @@ Rules Enforcing Blank Line Rule Group * `generate_003 <../generate_rules.html#generate-003>`_ * `generate_004 <../generate_rules.html#generate-004>`_ * `generic_019 <../generic_rules.html#generic-019>`_ +* `generic_map_201 <../generic_map_rules.html#generic-map-201>`_ * `if_006 <../if_rules.html#if-006>`_ * `if_007 <../if_rules.html#if-007>`_ * `if_008 <../if_rules.html#if-008>`_ @@ -69,6 +70,7 @@ Rules Enforcing Blank Line Rule Group * `port_022 <../port_rules.html#port-022>`_ * `port_024 <../port_rules.html#port-024>`_ * `port_map_200 <../port_map_rules.html#port-map-200>`_ +* `port_map_201 <../port_map_rules.html#port-map-201>`_ * `pragma_400 <../pragma_rules.html#pragma-400>`_ * `pragma_401 <../pragma_rules.html#pragma-401>`_ * `pragma_402 <../pragma_rules.html#pragma-402>`_ diff --git a/docs/whitespace_rules.rst b/docs/whitespace_rules.rst index 9083c0689..a7430e0bc 100644 --- a/docs/whitespace_rules.rst +++ b/docs/whitespace_rules.rst @@ -198,7 +198,7 @@ whitespace_011 |phase_2| |error| |whitespace| -This rule checks for at least a single space before and after math operators +, -, /, * and \*\*. +This rule checks for at least a single space before and after math operators +, -, /, * and **. **Violation** diff --git a/tests/generic_map/rule_201_test_input.fixed.vhd b/tests/generic_map/rule_201_test_input.fixed.vhd new file mode 100644 index 000000000..fbe9a58de --- /dev/null +++ b/tests/generic_map/rule_201_test_input.fixed.vhd @@ -0,0 +1,78 @@ + +architecture ARCH of ENTITY1 is + +begin + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + + PORT_3 => w_port_3 + ); + + -- Violations below + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + + PORT_3 => w_port_3 + ); + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + + ) + port map ( + + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + + PORT_3 => w_port_3 + ); + + -- Test with comments + + U_INST1 : INST1 + generic map ( + + -- Comment 1 + G_GEN_1 => 3, + G_GEN_2 => 4, + + -- Comment 2 + G_GEN_3 => 5 + + ) + port map ( + + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + + PORT_3 => w_port_3 + ); + + + +end architecture ARCH; diff --git a/tests/generic_map/rule_201_test_input.vhd b/tests/generic_map/rule_201_test_input.vhd new file mode 100644 index 000000000..1534d7fff --- /dev/null +++ b/tests/generic_map/rule_201_test_input.vhd @@ -0,0 +1,84 @@ + +architecture ARCH of ENTITY1 is + +begin + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + + PORT_3 => w_port_3 + ); + + -- Violations below + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + + PORT_3 => w_port_3 + ); + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + + G_GEN_2 => 4, + + G_GEN_3 => 5 + + ) + port map ( + + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + + PORT_3 => w_port_3 + ); + + -- Test with comments + + U_INST1 : INST1 + generic map ( + + -- Comment 1 + + G_GEN_1 => 3, + + G_GEN_2 => 4, + + -- Comment 2 + + G_GEN_3 => 5 + + ) + port map ( + + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + + PORT_3 => w_port_3 + ); + + + +end architecture ARCH; diff --git a/tests/generic_map/test_rule_201.py b/tests/generic_map/test_rule_201.py new file mode 100644 index 000000000..60849baca --- /dev/null +++ b/tests/generic_map/test_rule_201.py @@ -0,0 +1,46 @@ +# -*- coding: utf-8 -*- + +import os +import unittest + +from tests import utils +from vsg import vhdlFile +from vsg.rules import generic_map + +sTestDir = os.path.dirname(__file__) + +lFile, eError = vhdlFile.utils.read_vhdlfile(os.path.join(sTestDir, "rule_201_test_input.vhd")) + +lExpected = [] +lExpected.append("") +utils.read_file(os.path.join(sTestDir, "rule_201_test_input.fixed.vhd"), lExpected) + + +class test_generic_map_rule(unittest.TestCase): + def setUp(self): + self.oFile = vhdlFile.vhdlFile(lFile) + self.assertIsNone(eError) + + def test_rule_201(self): + oRule = generic_map.rule_201() + self.assertTrue(oRule) + self.assertEqual(oRule.name, "generic_map") + self.assertEqual(oRule.identifier, "201") + self.assertEqual(oRule.groups, ["blank_line"]) + + lExpected = [28, 43, 45, 64, 66, 70] + + oRule.analyze(self.oFile) + self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations)) + + def test_fix_rule_201(self): + oRule = generic_map.rule_201() + + oRule.fix(self.oFile) + + lActual = self.oFile.get_lines() + + self.assertEqual(lExpected, lActual) + + oRule.analyze(self.oFile) + self.assertEqual(oRule.violations, []) diff --git a/tests/port_map/rule_201_test_input.fixed.vhd b/tests/port_map/rule_201_test_input.fixed.vhd new file mode 100644 index 000000000..00cad71f2 --- /dev/null +++ b/tests/port_map/rule_201_test_input.fixed.vhd @@ -0,0 +1,76 @@ + +architecture ARCH of ENTITY1 is + +begin + + U_INST1 : INST1 + generic map ( + + G_GEN_1 => 3, + + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + -- Violations below + + U_INST1 : INST1 + generic map ( + + G_GEN_1 => 3, + + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + U_INST1 : INST1 + generic map ( + + G_GEN_1 => 3, + + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + -- Test with comments + + U_INST1 : INST1 + generic map ( + + G_GEN_1 => 3, + + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + + -- comment 1 + PORT_1 => w_port_1, + PORT_2 => w_port_2, + + -- comment 2 + PORT_3 => w_port_3 + ); + + + +end architecture ARCH; diff --git a/tests/port_map/rule_201_test_input.vhd b/tests/port_map/rule_201_test_input.vhd new file mode 100644 index 000000000..ee421dcd9 --- /dev/null +++ b/tests/port_map/rule_201_test_input.vhd @@ -0,0 +1,83 @@ + +architecture ARCH of ENTITY1 is + +begin + + U_INST1 : INST1 + generic map ( + + G_GEN_1 => 3, + + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + -- Violations below + + U_INST1 : INST1 + generic map ( + + G_GEN_1 => 3, + + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + U_INST1 : INST1 + generic map ( + + G_GEN_1 => 3, + + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + + + PORT_3 => w_port_3 + ); + + -- Test with comments + + U_INST1 : INST1 + generic map ( + + G_GEN_1 => 3, + + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + + -- comment 1 + + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + + -- comment 2 + + PORT_3 => w_port_3 + ); + + + +end architecture ARCH; diff --git a/tests/port_map/test_rule_201.py b/tests/port_map/test_rule_201.py new file mode 100644 index 000000000..ddfdc06db --- /dev/null +++ b/tests/port_map/test_rule_201.py @@ -0,0 +1,46 @@ +# -*- coding: utf-8 -*- + +import os +import unittest + +from tests import utils +from vsg import vhdlFile +from vsg.rules import port_map + +sTestDir = os.path.dirname(__file__) + +lFile, eError = vhdlFile.utils.read_vhdlfile(os.path.join(sTestDir, "rule_201_test_input.vhd")) + +lExpected = [] +lExpected.append("") +utils.read_file(os.path.join(sTestDir, "rule_201_test_input.fixed.vhd"), lExpected) + + +class test_port_map_rule(unittest.TestCase): + def setUp(self): + self.oFile = vhdlFile.vhdlFile(lFile) + self.assertIsNone(eError) + + def test_rule_201(self): + oRule = port_map.rule_201() + self.assertTrue(oRule) + self.assertEqual(oRule.name, "port_map") + self.assertEqual(oRule.identifier, "201") + self.assertEqual(oRule.groups, ["blank_line"]) + + lExpected = [35, 51, 54, 72, 74, 78] + + oRule.analyze(self.oFile) + self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations)) + + def test_fix_rule_201(self): + oRule = port_map.rule_201() + + oRule.fix(self.oFile) + + lActual = self.oFile.get_lines() + + self.assertEqual(lExpected, lActual) + + oRule.analyze(self.oFile) + self.assertEqual(oRule.violations, []) diff --git a/tests/rule_doc/test_rule_doc.py b/tests/rule_doc/test_rule_doc.py index 7e65fe8cb..879670d9f 100644 --- a/tests/rule_doc/test_rule_doc.py +++ b/tests/rule_doc/test_rule_doc.py @@ -15,6 +15,7 @@ def compare_files(cls, sRuleName): utils.read_file(os.path.join("docs", f"{sRuleName}_rules.rst"), lExpected, bStrip=False) lActual = [] utils.read_file(os.path.join(cls._tmpdir.name, f"{sRuleName}_rules.rst"), lActual, bStrip=False) + print(os.path.join(cls._tmpdir.name, f"{sRuleName}_rules.rst")) return lExpected, lActual @@ -77,6 +78,8 @@ def test_rule_link_in_configuration_documentation_exists(self): lActual.append(lLine[1][1:]) if sLine.startswith("Rules Enforcing"): bStartProcessing = True + if sKey == "configuring_blank_lines_link": + print("oui") self.assertEqual(dConfigurationFiles[sKey], lActual) def test_rule_link_in_configuration_documentation_for_underscores(self): @@ -124,6 +127,8 @@ def test_rule_group_links(self): lActual.append(lLine[1][1:]) if sLine.startswith("Rules Enforcing"): bStartProcessing = True + if sKey == "blank_line": + print("oui") self.assertEqual(dConfigurationFiles[sKey], lActual) def test_configuring_disabled_rules_doc(self): diff --git a/vsg/rules/generic_map/__init__.py b/vsg/rules/generic_map/__init__.py index 56cce9315..19c139664 100644 --- a/vsg/rules/generic_map/__init__.py +++ b/vsg/rules/generic_map/__init__.py @@ -11,6 +11,7 @@ from .rule_009 import rule_009 from .rule_100 import rule_100 from .rule_101 import rule_101 +from .rule_201 import rule_201 from .rule_300 import rule_300 from .rule_301 import rule_301 from .rule_302 import rule_302 diff --git a/vsg/rules/generic_map/rule_201.py b/vsg/rules/generic_map/rule_201.py new file mode 100644 index 000000000..9ea876368 --- /dev/null +++ b/vsg/rules/generic_map/rule_201.py @@ -0,0 +1,51 @@ +# -*- coding: utf-8 -*- + +from vsg import token +from vsg.rules.blank_line_above_line_starting_with_token_when_between_tokens import Rule + +lTokens = [] +lTokens.append(token.association_element.formal_part) + + +class rule_201(Rule): + """ + This rule checks for blank lines in a generic map. + + |configuring_blank_lines_link| + + **Violation** + + .. code-block:: vhdl + + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + **Fix** + + .. code-block:: vhdl + + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + """ + + def __init__(self): + super().__init__(lTokens) + self.style = "no_blank_line" + self.lBetweenTokenPairs = [token.generic_map_aspect.open_parenthesis, token.generic_map_aspect.close_parenthesis] diff --git a/vsg/rules/port_map/__init__.py b/vsg/rules/port_map/__init__.py index db1db362e..5b396220f 100644 --- a/vsg/rules/port_map/__init__.py +++ b/vsg/rules/port_map/__init__.py @@ -14,6 +14,7 @@ from .rule_100 import rule_100 from .rule_101 import rule_101 from .rule_200 import rule_200 +from .rule_201 import rule_201 from .rule_300 import rule_300 from .rule_301 import rule_301 from .rule_302 import rule_302 diff --git a/vsg/rules/port_map/rule_201.py b/vsg/rules/port_map/rule_201.py new file mode 100644 index 000000000..22b644023 --- /dev/null +++ b/vsg/rules/port_map/rule_201.py @@ -0,0 +1,52 @@ +# -*- coding: utf-8 -*- + +from vsg import token +from vsg.rules.blank_line_above_line_starting_with_token_when_between_tokens import Rule + +lTokens = [] +lTokens.append(token.association_element.formal_part) + + +class rule_201(Rule): + """ + This rule checks for blank lines in a port map. + + |configuring_blank_lines_link| + + **Violation** + + .. code-block:: vhdl + + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + **Fix** + + .. code-block:: vhdl + + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + """ + + def __init__(self): + super().__init__(lTokens) + self.style = "no_blank_line" + self.lBetweenTokenPairs = [token.port_map_aspect.open_parenthesis, token.port_map_aspect.close_parenthesis] diff --git a/vsg/rules/whitespace/rule_011.py b/vsg/rules/whitespace/rule_011.py index b20bf0fa3..7a5fc9079 100644 --- a/vsg/rules/whitespace/rule_011.py +++ b/vsg/rules/whitespace/rule_011.py @@ -13,7 +13,7 @@ class rule_011(n_spaces_before_and_after_tokens): r""" - This rule checks for at least a single space before and after math operators +, -, /, * and \*\*. + This rule checks for at least a single space before and after math operators +, -, /, * and **. **Violation** diff --git a/vsg/styles/jcl.yaml b/vsg/styles/jcl.yaml index a276bba78..fd05d1d61 100644 --- a/vsg/styles/jcl.yaml +++ b/vsg/styles/jcl.yaml @@ -104,3 +104,7 @@ rule : interface_list_semicolon: 'remove_new_line' interface_element: 'add_new_line' ignore_single_line: 'yes' + port_map_201: + disable: True + generic_map_201: + disable: True