From ee49336cf902cb2dbef4c61b4e0ae95e891b50fe Mon Sep 17 00:00:00 2001 From: Loan Guilbaud Date: Wed, 30 Apr 2025 11:49:32 +0200 Subject: [PATCH 01/10] Add rule_201 for port_map rules --- docs/port_map_rules.rst | 31 +++++++++++++ tests/port_map/rule_201_test_input.fixed.vhd | 45 ++++++++++++++++++ tests/port_map/rule_201_test_input.vhd | 49 ++++++++++++++++++++ tests/port_map/test_rule_201.py | 49 ++++++++++++++++++++ vsg/rules/port_map/rule_201.py | 38 +++++++++++++++ 5 files changed, 212 insertions(+) create mode 100644 tests/port_map/rule_201_test_input.fixed.vhd create mode 100644 tests/port_map/rule_201_test_input.vhd create mode 100644 tests/port_map/test_rule_201.py create mode 100644 vsg/rules/port_map/rule_201.py diff --git a/docs/port_map_rules.rst b/docs/port_map_rules.rst index ce9ad01e3..7708ba0c4 100644 --- a/docs/port_map_rules.rst +++ b/docs/port_map_rules.rst @@ -383,6 +383,37 @@ This rule checks for a blank line below the open parenthesis in a port map. OVERFLOW => w_overflow ); +port_map_201 +############ + +|phase_3| |error| |blank_line| + +This rule checks for blank lines in a port map. + +|configuring_blank_lines_link| + +**Violation** + +.. code-block:: vhdl + + port map ( + WR_EN => w_wr_en, + + RD_EN => w_rd_en, + OVERFLOW => w_overflow + ); + +**Fix** + +.. code-block:: vhdl + + port map ( + WR_EN => w_wr_en, + RD_EN => w_rd_en, + OVERFLOW => w_overflow + ); + + port_map_300 ############ diff --git a/tests/port_map/rule_201_test_input.fixed.vhd b/tests/port_map/rule_201_test_input.fixed.vhd new file mode 100644 index 000000000..2239a4ec0 --- /dev/null +++ b/tests/port_map/rule_201_test_input.fixed.vhd @@ -0,0 +1,45 @@ + +architecture ARCH of ENTITY1 is + +begin + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + -- Violations below + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + +end architecture ARCH; diff --git a/tests/port_map/rule_201_test_input.vhd b/tests/port_map/rule_201_test_input.vhd new file mode 100644 index 000000000..dcd73be52 --- /dev/null +++ b/tests/port_map/rule_201_test_input.vhd @@ -0,0 +1,49 @@ + +architecture ARCH of ENTITY1 is + +begin + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + -- Violations below + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + + + PORT_3 => w_port_3 + ); + + +end architecture ARCH; diff --git a/tests/port_map/test_rule_201.py b/tests/port_map/test_rule_201.py new file mode 100644 index 000000000..99f6b07d4 --- /dev/null +++ b/tests/port_map/test_rule_201.py @@ -0,0 +1,49 @@ +# -*- coding: utf-8 -*- + +import os +import unittest + +from tests import utils +from vsg import vhdlFile +from vsg.rules import port_map + +sTestDir = os.path.dirname(__file__) + +lFile, eError = vhdlFile.utils.read_vhdlfile(os.path.join(sTestDir, "rule_201_test_input.vhd")) + +lExpected = [] +lExpected.append("") +utils.read_file(os.path.join(sTestDir, "rule_201_test_input.fixed.vhd"), lExpected) + + +class test_port_map_rule(unittest.TestCase): + + maxDiff = None + + def setUp(self): + self.oFile = vhdlFile.vhdlFile(lFile) + self.assertIsNone(eError) + + def test_rule_201(self): + oRule = port_map.rule_201() + self.assertTrue(oRule) + self.assertEqual(oRule.name, "port_map") + self.assertEqual(oRule.identifier, "201") + self.assertEqual(oRule.groups, ["blank_line"]) + + lExpected = [28, 41, 43, 44] + + oRule.analyze(self.oFile) + self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations)) + + def test_fix_rule_201(self): + oRule = port_map.rule_201() + + oRule.fix(self.oFile) + + lActual = self.oFile.get_lines() + + self.assertEqual(lExpected, lActual) + + oRule.analyze(self.oFile) + self.assertEqual(oRule.violations, []) diff --git a/vsg/rules/port_map/rule_201.py b/vsg/rules/port_map/rule_201.py new file mode 100644 index 000000000..b0690da2f --- /dev/null +++ b/vsg/rules/port_map/rule_201.py @@ -0,0 +1,38 @@ +# -*- coding: utf-8 -*- + +from vsg import token +from vsg.rules import blank_lines_between_token_pairs as Rule + +lTokenPairs = [] +lTokenPairs.append([token.port_map_aspect.open_parenthesis, token.port_map_aspect.close_parenthesis]) + +class rule_201(Rule): + """ + This rule checks for blank lines in a port map. + + |configuring_blank_lines_link| + + **Violation** + + .. code-block:: vhdl + + port map ( + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + **Fix** + + .. code-block:: vhdl + + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + """ + + def __init__(self): + super().__init__(lTokenPairs) From f2ee17ec69437bfaa9c8a82446822518b75756cd Mon Sep 17 00:00:00 2001 From: Loan Guilbaud Date: Wed, 30 Apr 2025 11:50:06 +0200 Subject: [PATCH 02/10] Forgot __init__ file --- vsg/rules/port_map/__init__.py | 1 + 1 file changed, 1 insertion(+) diff --git a/vsg/rules/port_map/__init__.py b/vsg/rules/port_map/__init__.py index db1db362e..5b396220f 100644 --- a/vsg/rules/port_map/__init__.py +++ b/vsg/rules/port_map/__init__.py @@ -14,6 +14,7 @@ from .rule_100 import rule_100 from .rule_101 import rule_101 from .rule_200 import rule_200 +from .rule_201 import rule_201 from .rule_300 import rule_300 from .rule_301 import rule_301 from .rule_302 import rule_302 From 9e27755bb4dd8b5914e410e9029488809f7733b5 Mon Sep 17 00:00:00 2001 From: Loan Guilbaud Date: Wed, 30 Apr 2025 13:18:24 +0200 Subject: [PATCH 03/10] Fix tests with errors --- docs/configuring_blank_lines.rst | 1 + docs/port_map_rules.rst | 22 ++++++++++++++++------ docs/rule_groups/blank_line_rule_group.rst | 1 + vsg/rules/port_map/rule_201.py | 21 ++++++++++++++++----- 4 files changed, 34 insertions(+), 11 deletions(-) diff --git a/docs/configuring_blank_lines.rst b/docs/configuring_blank_lines.rst index f052e7904..d4fd59a94 100644 --- a/docs/configuring_blank_lines.rst +++ b/docs/configuring_blank_lines.rst @@ -169,6 +169,7 @@ Rules Enforcing Blank Lines * `package_instantiation_201 `_ * `port_001 `_ * `port_map_200 `_ +* `port_map_201 `_ * `pragma_401 `_ * `pragma_403 `_ * `process_011 `_ diff --git a/docs/port_map_rules.rst b/docs/port_map_rules.rst index 7708ba0c4..c9fc82ff8 100644 --- a/docs/port_map_rules.rst +++ b/docs/port_map_rules.rst @@ -396,21 +396,31 @@ This rule checks for blank lines in a port map. .. code-block:: vhdl + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) port map ( - WR_EN => w_wr_en, + PORT_1 => w_port_1, - RD_EN => w_rd_en, - OVERFLOW => w_overflow + PORT_2 => w_port_2, + PORT_3 => w_port_3 ); **Fix** .. code-block:: vhdl + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) port map ( - WR_EN => w_wr_en, - RD_EN => w_rd_en, - OVERFLOW => w_overflow + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 ); diff --git a/docs/rule_groups/blank_line_rule_group.rst b/docs/rule_groups/blank_line_rule_group.rst index 143d181e6..11bc2e443 100644 --- a/docs/rule_groups/blank_line_rule_group.rst +++ b/docs/rule_groups/blank_line_rule_group.rst @@ -69,6 +69,7 @@ Rules Enforcing Blank Line Rule Group * `port_022 <../port_rules.html#port-022>`_ * `port_024 <../port_rules.html#port-024>`_ * `port_map_200 <../port_map_rules.html#port-map-200>`_ +* `port_map_201 <../port_map_rules.html#port-map-201>`_ * `pragma_400 <../pragma_rules.html#pragma-400>`_ * `pragma_401 <../pragma_rules.html#pragma-401>`_ * `pragma_402 <../pragma_rules.html#pragma-402>`_ diff --git a/vsg/rules/port_map/rule_201.py b/vsg/rules/port_map/rule_201.py index b0690da2f..bf97d534c 100644 --- a/vsg/rules/port_map/rule_201.py +++ b/vsg/rules/port_map/rule_201.py @@ -16,22 +16,33 @@ class rule_201(Rule): .. code-block:: vhdl + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 - ); + ); **Fix** .. code-block:: vhdl + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) port map ( - PORT_1 => w_port_1, - PORT_2 => w_port_2, - PORT_3 => w_port_3 - ); + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + """ def __init__(self): From b4ac4cd030fd70fb019abf4b80d1f121c39c355e Mon Sep 17 00:00:00 2001 From: Loan Guilbaud Date: Wed, 7 May 2025 13:57:10 +0200 Subject: [PATCH 04/10] Add generic_map_201 identical to port_map_201 --- docs/configuring_blank_lines.rst | 1 + docs/generic_map_rules.rst | 40 +++++++++++++++ docs/rule_groups/blank_line_rule_group.rst | 1 + .../generic_map/rule_201_test_input.fixed.vhd | 45 +++++++++++++++++ tests/generic_map/rule_201_test_input.vhd | 49 +++++++++++++++++++ tests/generic_map/test_rule_201.py | 49 +++++++++++++++++++ tests/rule_doc/test_rule_doc.py | 5 ++ vsg/rules/generic_map/__init__.py | 1 + vsg/rules/generic_map/rule_201.py | 48 ++++++++++++++++++ 9 files changed, 239 insertions(+) create mode 100644 tests/generic_map/rule_201_test_input.fixed.vhd create mode 100644 tests/generic_map/rule_201_test_input.vhd create mode 100644 tests/generic_map/test_rule_201.py create mode 100644 vsg/rules/generic_map/rule_201.py diff --git a/docs/configuring_blank_lines.rst b/docs/configuring_blank_lines.rst index d4fd59a94..f1b0e83ba 100644 --- a/docs/configuring_blank_lines.rst +++ b/docs/configuring_blank_lines.rst @@ -157,6 +157,7 @@ Rules Enforcing Blank Lines * `entity_202 `_ * `entity_203 `_ * `generate_003 `_ +* `generic_map_201 `_ * `if_030 `_ * `instantiation_019 `_ * `loop_statement_201 `_ diff --git a/docs/generic_map_rules.rst b/docs/generic_map_rules.rst index c7a1c4f7e..4d3cedfd3 100644 --- a/docs/generic_map_rules.rst +++ b/docs/generic_map_rules.rst @@ -292,6 +292,46 @@ This rule checks for a single space between the **generic** keyword and the **ma generic map ( +generic_map_201 +############### + +|phase_3| |error| |blank_line| + +This rule checks for blank lines in a generic map. + +|configuring_blank_lines_link| + +**Violation** + +.. code-block:: vhdl + + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + +**Fix** + +.. code-block:: vhdl + + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + generic_map_300 ############### diff --git a/docs/rule_groups/blank_line_rule_group.rst b/docs/rule_groups/blank_line_rule_group.rst index 11bc2e443..75502dd6c 100644 --- a/docs/rule_groups/blank_line_rule_group.rst +++ b/docs/rule_groups/blank_line_rule_group.rst @@ -41,6 +41,7 @@ Rules Enforcing Blank Line Rule Group * `generate_003 <../generate_rules.html#generate-003>`_ * `generate_004 <../generate_rules.html#generate-004>`_ * `generic_019 <../generic_rules.html#generic-019>`_ +* `generic_map_201 <../generic_map_rules.html#generic-map-201>`_ * `if_006 <../if_rules.html#if-006>`_ * `if_007 <../if_rules.html#if-007>`_ * `if_008 <../if_rules.html#if-008>`_ diff --git a/tests/generic_map/rule_201_test_input.fixed.vhd b/tests/generic_map/rule_201_test_input.fixed.vhd new file mode 100644 index 000000000..2239a4ec0 --- /dev/null +++ b/tests/generic_map/rule_201_test_input.fixed.vhd @@ -0,0 +1,45 @@ + +architecture ARCH of ENTITY1 is + +begin + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + -- Violations below + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + +end architecture ARCH; diff --git a/tests/generic_map/rule_201_test_input.vhd b/tests/generic_map/rule_201_test_input.vhd new file mode 100644 index 000000000..d376f2331 --- /dev/null +++ b/tests/generic_map/rule_201_test_input.vhd @@ -0,0 +1,49 @@ + +architecture ARCH of ENTITY1 is + +begin + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + -- Violations below + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + + G_GEN_2 => 4, + + G_GEN_3 => 5 + + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + +end architecture ARCH; diff --git a/tests/generic_map/test_rule_201.py b/tests/generic_map/test_rule_201.py new file mode 100644 index 000000000..51e52d881 --- /dev/null +++ b/tests/generic_map/test_rule_201.py @@ -0,0 +1,49 @@ +# -*- coding: utf-8 -*- + +import os +import unittest + +from tests import utils +from vsg import vhdlFile +from vsg.rules import generic_map + +sTestDir = os.path.dirname(__file__) + +lFile, eError = vhdlFile.utils.read_vhdlfile(os.path.join(sTestDir, "rule_201_test_input.vhd")) + +lExpected = [] +lExpected.append("") +utils.read_file(os.path.join(sTestDir, "rule_201_test_input.fixed.vhd"), lExpected) + + +class test_generic_map_rule(unittest.TestCase): + + maxDiff = None + + def setUp(self): + self.oFile = vhdlFile.vhdlFile(lFile) + self.assertIsNone(eError) + + def test_rule_201(self): + oRule = generic_map.rule_201() + self.assertTrue(oRule) + self.assertEqual(oRule.name, "generic_map") + self.assertEqual(oRule.identifier, "201") + self.assertEqual(oRule.groups, ["blank_line"]) + + lExpected = [24, 36, 38, 40] + + oRule.analyze(self.oFile) + self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations)) + + def test_fix_rule_201(self): + oRule = generic_map.rule_201() + + oRule.fix(self.oFile) + + lActual = self.oFile.get_lines() + + self.assertEqual(lExpected, lActual) + + oRule.analyze(self.oFile) + self.assertEqual(oRule.violations, []) diff --git a/tests/rule_doc/test_rule_doc.py b/tests/rule_doc/test_rule_doc.py index 7e65fe8cb..879670d9f 100644 --- a/tests/rule_doc/test_rule_doc.py +++ b/tests/rule_doc/test_rule_doc.py @@ -15,6 +15,7 @@ def compare_files(cls, sRuleName): utils.read_file(os.path.join("docs", f"{sRuleName}_rules.rst"), lExpected, bStrip=False) lActual = [] utils.read_file(os.path.join(cls._tmpdir.name, f"{sRuleName}_rules.rst"), lActual, bStrip=False) + print(os.path.join(cls._tmpdir.name, f"{sRuleName}_rules.rst")) return lExpected, lActual @@ -77,6 +78,8 @@ def test_rule_link_in_configuration_documentation_exists(self): lActual.append(lLine[1][1:]) if sLine.startswith("Rules Enforcing"): bStartProcessing = True + if sKey == "configuring_blank_lines_link": + print("oui") self.assertEqual(dConfigurationFiles[sKey], lActual) def test_rule_link_in_configuration_documentation_for_underscores(self): @@ -124,6 +127,8 @@ def test_rule_group_links(self): lActual.append(lLine[1][1:]) if sLine.startswith("Rules Enforcing"): bStartProcessing = True + if sKey == "blank_line": + print("oui") self.assertEqual(dConfigurationFiles[sKey], lActual) def test_configuring_disabled_rules_doc(self): diff --git a/vsg/rules/generic_map/__init__.py b/vsg/rules/generic_map/__init__.py index 56cce9315..19c139664 100644 --- a/vsg/rules/generic_map/__init__.py +++ b/vsg/rules/generic_map/__init__.py @@ -11,6 +11,7 @@ from .rule_009 import rule_009 from .rule_100 import rule_100 from .rule_101 import rule_101 +from .rule_201 import rule_201 from .rule_300 import rule_300 from .rule_301 import rule_301 from .rule_302 import rule_302 diff --git a/vsg/rules/generic_map/rule_201.py b/vsg/rules/generic_map/rule_201.py new file mode 100644 index 000000000..c237c0803 --- /dev/null +++ b/vsg/rules/generic_map/rule_201.py @@ -0,0 +1,48 @@ +# -*- coding: utf-8 -*- + +from vsg import token +from vsg.rules import blank_lines_between_token_pairs as Rule + +lTokenPairs = [] +lTokenPairs.append([token.generic_map_aspect.open_parenthesis, token.generic_map_aspect.close_parenthesis]) + +class rule_201(Rule): + """ + This rule checks for blank lines in a generic map. + + |configuring_blank_lines_link| + + **Violation** + + .. code-block:: vhdl + + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + **Fix** + + .. code-block:: vhdl + + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + """ + + def __init__(self): + super().__init__(lTokenPairs) From 2666398bea35bb78d833971e42c0e833719364aa Mon Sep 17 00:00:00 2001 From: Loan Guilbaud Date: Wed, 7 May 2025 13:58:19 +0200 Subject: [PATCH 05/10] Remove maxDiff --- tests/generic_map/test_rule_201.py | 2 -- tests/port_map/test_rule_201.py | 2 -- 2 files changed, 4 deletions(-) diff --git a/tests/generic_map/test_rule_201.py b/tests/generic_map/test_rule_201.py index 51e52d881..ba992d5e3 100644 --- a/tests/generic_map/test_rule_201.py +++ b/tests/generic_map/test_rule_201.py @@ -18,8 +18,6 @@ class test_generic_map_rule(unittest.TestCase): - maxDiff = None - def setUp(self): self.oFile = vhdlFile.vhdlFile(lFile) self.assertIsNone(eError) diff --git a/tests/port_map/test_rule_201.py b/tests/port_map/test_rule_201.py index 99f6b07d4..373a5f8e7 100644 --- a/tests/port_map/test_rule_201.py +++ b/tests/port_map/test_rule_201.py @@ -18,8 +18,6 @@ class test_port_map_rule(unittest.TestCase): - maxDiff = None - def setUp(self): self.oFile = vhdlFile.vhdlFile(lFile) self.assertIsNone(eError) From 0829f5c2a676dd5c15edc53c3126cdc564ac14d2 Mon Sep 17 00:00:00 2001 From: Jeremiah Leary Date: Mon, 1 Sep 2025 10:44:43 -0500 Subject: [PATCH 06/10] Disabling new rules for jcl style. --- vsg/styles/jcl.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/vsg/styles/jcl.yaml b/vsg/styles/jcl.yaml index a276bba78..fd05d1d61 100644 --- a/vsg/styles/jcl.yaml +++ b/vsg/styles/jcl.yaml @@ -104,3 +104,7 @@ rule : interface_list_semicolon: 'remove_new_line' interface_element: 'add_new_line' ignore_single_line: 'yes' + port_map_201: + disable: True + generic_map_201: + disable: True From 0736f74cfee19f186c898b0a8dfac79c939b4621 Mon Sep 17 00:00:00 2001 From: Jeremiah Leary Date: Mon, 1 Sep 2025 10:50:14 -0500 Subject: [PATCH 07/10] Fixing style issues. --- tests/generic_map/test_rule_201.py | 1 - tests/port_map/test_rule_201.py | 1 - vsg/rules/generic_map/rule_201.py | 1 + vsg/rules/port_map/rule_201.py | 1 + 4 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/generic_map/test_rule_201.py b/tests/generic_map/test_rule_201.py index ba992d5e3..983f77943 100644 --- a/tests/generic_map/test_rule_201.py +++ b/tests/generic_map/test_rule_201.py @@ -17,7 +17,6 @@ class test_generic_map_rule(unittest.TestCase): - def setUp(self): self.oFile = vhdlFile.vhdlFile(lFile) self.assertIsNone(eError) diff --git a/tests/port_map/test_rule_201.py b/tests/port_map/test_rule_201.py index 373a5f8e7..695b4273d 100644 --- a/tests/port_map/test_rule_201.py +++ b/tests/port_map/test_rule_201.py @@ -17,7 +17,6 @@ class test_port_map_rule(unittest.TestCase): - def setUp(self): self.oFile = vhdlFile.vhdlFile(lFile) self.assertIsNone(eError) diff --git a/vsg/rules/generic_map/rule_201.py b/vsg/rules/generic_map/rule_201.py index c237c0803..30f7bdad9 100644 --- a/vsg/rules/generic_map/rule_201.py +++ b/vsg/rules/generic_map/rule_201.py @@ -6,6 +6,7 @@ lTokenPairs = [] lTokenPairs.append([token.generic_map_aspect.open_parenthesis, token.generic_map_aspect.close_parenthesis]) + class rule_201(Rule): """ This rule checks for blank lines in a generic map. diff --git a/vsg/rules/port_map/rule_201.py b/vsg/rules/port_map/rule_201.py index bf97d534c..a5e33aab3 100644 --- a/vsg/rules/port_map/rule_201.py +++ b/vsg/rules/port_map/rule_201.py @@ -6,6 +6,7 @@ lTokenPairs = [] lTokenPairs.append([token.port_map_aspect.open_parenthesis, token.port_map_aspect.close_parenthesis]) + class rule_201(Rule): """ This rule checks for blank lines in a port map. From 585486a5c0b834be6660d7dcf4b389af2a1c2e4b Mon Sep 17 00:00:00 2001 From: Jeremiah Leary Date: Mon, 1 Sep 2025 12:25:20 -0500 Subject: [PATCH 08/10] Updating rules to take comments into account. --- .../generic_map/rule_201_test_input.fixed.vhd | 33 +++++++++++++++++ tests/generic_map/rule_201_test_input.vhd | 35 +++++++++++++++++++ tests/generic_map/test_rule_201.py | 2 +- tests/port_map/rule_201_test_input.fixed.vhd | 31 ++++++++++++++++ tests/port_map/rule_201_test_input.vhd | 34 ++++++++++++++++++ tests/port_map/test_rule_201.py | 2 +- vsg/rules/generic_map/rule_201.py | 10 +++--- vsg/rules/port_map/rule_201.py | 10 +++--- 8 files changed, 147 insertions(+), 10 deletions(-) diff --git a/tests/generic_map/rule_201_test_input.fixed.vhd b/tests/generic_map/rule_201_test_input.fixed.vhd index 2239a4ec0..fbe9a58de 100644 --- a/tests/generic_map/rule_201_test_input.fixed.vhd +++ b/tests/generic_map/rule_201_test_input.fixed.vhd @@ -10,8 +10,11 @@ begin G_GEN_3 => 5 ) port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 ); @@ -24,22 +27,52 @@ begin G_GEN_3 => 5 ) port map ( + + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + + PORT_3 => w_port_3 + ); + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 + + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 ); + -- Test with comments + U_INST1 : INST1 generic map ( + + -- Comment 1 G_GEN_1 => 3, G_GEN_2 => 4, + + -- Comment 2 G_GEN_3 => 5 + ) port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 ); + end architecture ARCH; diff --git a/tests/generic_map/rule_201_test_input.vhd b/tests/generic_map/rule_201_test_input.vhd index d376f2331..1534d7fff 100644 --- a/tests/generic_map/rule_201_test_input.vhd +++ b/tests/generic_map/rule_201_test_input.vhd @@ -10,8 +10,11 @@ begin G_GEN_3 => 5 ) port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 ); @@ -25,25 +28,57 @@ begin G_GEN_3 => 5 ) port map ( + + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + + PORT_3 => w_port_3 + ); + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + + G_GEN_2 => 4, + + G_GEN_3 => 5 + + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 ); + -- Test with comments + U_INST1 : INST1 generic map ( + + -- Comment 1 + G_GEN_1 => 3, G_GEN_2 => 4, + -- Comment 2 + G_GEN_3 => 5 ) port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 ); + end architecture ARCH; diff --git a/tests/generic_map/test_rule_201.py b/tests/generic_map/test_rule_201.py index 983f77943..60849baca 100644 --- a/tests/generic_map/test_rule_201.py +++ b/tests/generic_map/test_rule_201.py @@ -28,7 +28,7 @@ def test_rule_201(self): self.assertEqual(oRule.identifier, "201") self.assertEqual(oRule.groups, ["blank_line"]) - lExpected = [24, 36, 38, 40] + lExpected = [28, 43, 45, 64, 66, 70] oRule.analyze(self.oFile) self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations)) diff --git a/tests/port_map/rule_201_test_input.fixed.vhd b/tests/port_map/rule_201_test_input.fixed.vhd index 2239a4ec0..00cad71f2 100644 --- a/tests/port_map/rule_201_test_input.fixed.vhd +++ b/tests/port_map/rule_201_test_input.fixed.vhd @@ -5,8 +5,11 @@ begin U_INST1 : INST1 generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 ) port map ( @@ -19,8 +22,26 @@ begin U_INST1 : INST1 generic map ( + + G_GEN_1 => 3, + + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + PORT_1 => w_port_1, + PORT_2 => w_port_2, + PORT_3 => w_port_3 + ); + + U_INST1 : INST1 + generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 ) port map ( @@ -29,17 +50,27 @@ begin PORT_3 => w_port_3 ); + -- Test with comments + U_INST1 : INST1 generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 ) port map ( + + -- comment 1 PORT_1 => w_port_1, PORT_2 => w_port_2, + + -- comment 2 PORT_3 => w_port_3 ); + end architecture ARCH; diff --git a/tests/port_map/rule_201_test_input.vhd b/tests/port_map/rule_201_test_input.vhd index dcd73be52..ee421dcd9 100644 --- a/tests/port_map/rule_201_test_input.vhd +++ b/tests/port_map/rule_201_test_input.vhd @@ -5,8 +5,11 @@ begin U_INST1 : INST1 generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 ) port map ( @@ -19,8 +22,11 @@ begin U_INST1 : INST1 generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 ) port map ( @@ -32,8 +38,11 @@ begin U_INST1 : INST1 generic map ( + G_GEN_1 => 3, + G_GEN_2 => 4, + G_GEN_3 => 5 ) port map ( @@ -45,5 +54,30 @@ begin PORT_3 => w_port_3 ); + -- Test with comments + + U_INST1 : INST1 + generic map ( + + G_GEN_1 => 3, + + G_GEN_2 => 4, + + G_GEN_3 => 5 + ) + port map ( + + -- comment 1 + + PORT_1 => w_port_1, + + PORT_2 => w_port_2, + + -- comment 2 + + PORT_3 => w_port_3 + ); + + end architecture ARCH; diff --git a/tests/port_map/test_rule_201.py b/tests/port_map/test_rule_201.py index 695b4273d..ddfdc06db 100644 --- a/tests/port_map/test_rule_201.py +++ b/tests/port_map/test_rule_201.py @@ -28,7 +28,7 @@ def test_rule_201(self): self.assertEqual(oRule.identifier, "201") self.assertEqual(oRule.groups, ["blank_line"]) - lExpected = [28, 41, 43, 44] + lExpected = [35, 51, 54, 72, 74, 78] oRule.analyze(self.oFile) self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations)) diff --git a/vsg/rules/generic_map/rule_201.py b/vsg/rules/generic_map/rule_201.py index 30f7bdad9..9ea876368 100644 --- a/vsg/rules/generic_map/rule_201.py +++ b/vsg/rules/generic_map/rule_201.py @@ -1,10 +1,10 @@ # -*- coding: utf-8 -*- from vsg import token -from vsg.rules import blank_lines_between_token_pairs as Rule +from vsg.rules.blank_line_above_line_starting_with_token_when_between_tokens import Rule -lTokenPairs = [] -lTokenPairs.append([token.generic_map_aspect.open_parenthesis, token.generic_map_aspect.close_parenthesis]) +lTokens = [] +lTokens.append(token.association_element.formal_part) class rule_201(Rule): @@ -46,4 +46,6 @@ class rule_201(Rule): """ def __init__(self): - super().__init__(lTokenPairs) + super().__init__(lTokens) + self.style = "no_blank_line" + self.lBetweenTokenPairs = [token.generic_map_aspect.open_parenthesis, token.generic_map_aspect.close_parenthesis] diff --git a/vsg/rules/port_map/rule_201.py b/vsg/rules/port_map/rule_201.py index a5e33aab3..22b644023 100644 --- a/vsg/rules/port_map/rule_201.py +++ b/vsg/rules/port_map/rule_201.py @@ -1,10 +1,10 @@ # -*- coding: utf-8 -*- from vsg import token -from vsg.rules import blank_lines_between_token_pairs as Rule +from vsg.rules.blank_line_above_line_starting_with_token_when_between_tokens import Rule -lTokenPairs = [] -lTokenPairs.append([token.port_map_aspect.open_parenthesis, token.port_map_aspect.close_parenthesis]) +lTokens = [] +lTokens.append(token.association_element.formal_part) class rule_201(Rule): @@ -47,4 +47,6 @@ class rule_201(Rule): """ def __init__(self): - super().__init__(lTokenPairs) + super().__init__(lTokens) + self.style = "no_blank_line" + self.lBetweenTokenPairs = [token.port_map_aspect.open_parenthesis, token.port_map_aspect.close_parenthesis] From 0b94ad0136392aa24e2ed7eabba3be6a3de25848 Mon Sep 17 00:00:00 2001 From: Rui Chen Date: Mon, 1 Sep 2025 11:01:30 -0400 Subject: [PATCH 09/10] fix SyntaxWarning for py3.13 compatibility (#1441) Signed-off-by: Rui Chen --- vsg/rules/whitespace/rule_011.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vsg/rules/whitespace/rule_011.py b/vsg/rules/whitespace/rule_011.py index b20bf0fa3..7a5fc9079 100644 --- a/vsg/rules/whitespace/rule_011.py +++ b/vsg/rules/whitespace/rule_011.py @@ -13,7 +13,7 @@ class rule_011(n_spaces_before_and_after_tokens): r""" - This rule checks for at least a single space before and after math operators +, -, /, * and \*\*. + This rule checks for at least a single space before and after math operators +, -, /, * and **. **Violation** From ac04129769b493937cbd5c4057c5dc68f009c875 Mon Sep 17 00:00:00 2001 From: Jeremiah Leary Date: Mon, 1 Sep 2025 12:56:40 -0500 Subject: [PATCH 10/10] Fixing test failure on documentation. --- docs/whitespace_rules.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/whitespace_rules.rst b/docs/whitespace_rules.rst index 9083c0689..a7430e0bc 100644 --- a/docs/whitespace_rules.rst +++ b/docs/whitespace_rules.rst @@ -198,7 +198,7 @@ whitespace_011 |phase_2| |error| |whitespace| -This rule checks for at least a single space before and after math operators +, -, /, * and \*\*. +This rule checks for at least a single space before and after math operators +, -, /, * and **. **Violation**