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DiyouSDiyouS
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[TB] Change testbench frequency to 1GHz; Add customized DDR configurations.
1 parent 78306df commit 969042d

10 files changed

Lines changed: 270 additions & 9 deletions

‎Makefile‎

Lines changed: 47 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,9 @@ SPATZ_DIR ?= ${DEP_DIR}/spatz
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SPZ_CLS_DIR ?= ${SPATZ_DIR}/hw/system/spatz_cluster
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### DramSys
4343
DRAMSYS_DIR ?= ${DEP_DIR}/dram_rtl_sim
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DRAMSYS_LIB_PATH ?= ${DRAMSYS_DIR}/dramsys_lib/DRAMSys/build/lib
45-
DRAMSYS_RES_PATH ?= ${DRAMSYS_DIR}/dramsys_lib/DRAMSys/configs
44+
DRAMSYS_PATH := ${DRAMSYS_DIR}/dramsys_lib/DRAMSys
45+
DRAMSYS_LIB_PATH := ${DRAMSYS_PATH}/build/lib
46+
DRAMSYS_RES_PATH := ${DRAMSYS_PATH}/configs
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4748
## Software subpaths
4849
SPATZ_SW_DIR ?= ${SPATZ_DIR}/sw
@@ -54,7 +55,9 @@ SNLIB_DIR ?= ${SPATZ_DIR}/hw/ip/snitch_test/src
5455
BOOTLIB_DIR := ${SPZ_CLS_DIR}/test
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WORK_DIR := ${SIM_DIR}/work
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SIMBIN_DIR := ${SIM_DIR}/bin
57-
DPI_PATH := ${HARDWARE_DIR}/tb/dpi
58+
TB_DIR := ${HARDWARE_DIR}/tb
59+
DPI_PATH := ${TB_DIR}/dpi
60+
DRAM_CFG_PATH := ${TB_DIR}/dram_config
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DPI_LIB ?= work-dpi
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# Set to 0 will turn off +acc target for faster simulation
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DEBUG ?= 1
@@ -140,8 +143,6 @@ else
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@echo "insitu-cache path unavailable (bender not installed yet?)"
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endif
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143-
# Paths
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# Paths
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BOOTROM_DIR := $(HARDWARE_DIR)/bootrom
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SCRIPTS_DIR := $(CACHEPOOL_DIR)/util/scripts
@@ -192,9 +193,47 @@ VSIM_FLAGS :=
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VSIM_BENDER =
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194195
## Build DramSys
195-
.PHONY: dram-build
196-
dram-build:
197-
$(MAKE) -BC ${DRAMSYS_DIR} -j8 dramsys CXX=$(CXX) CC=$(CC)
196+
# .PHONY: dram-build
197+
# dram-build:
198+
# $(MAKE) -BC ${DRAMSYS_DIR} -j8 dramsys CXX=$(CXX) CC=$(CC)
199+
dram-build: $(DRAMSYS_PATH)/README.md dram-clean dram-config
200+
cd $(DRAMSYS_PATH) && \
201+
if [ ! -d "build" ]; then \
202+
mkdir build && cd build; \
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$(CMAKE) -DCMAKE_CXX_FLAGS=-fPIC -DCMAKE_C_FLAGS=-fPIC -D DRAMSYS_WITH_DRAMPOWER=ON .. ; \
204+
make -j; \
205+
fi
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$(DRAMSYS_PATH)/README.md: dram-init
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# Replace the default HBM2 model to cutmized model
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dram-config:
211+
cp $(DRAM_CFG_PATH)/am_hbm2e_16Gb_pc_brc.json $(DRAMSYS_PATH)/configs/addressmapping/.
212+
cp $(DRAM_CFG_PATH)/mc_hbm2e_fr_fcfs_grp.json $(DRAMSYS_PATH)/configs/mcconfig/.
213+
cp $(DRAM_CFG_PATH)/ms_hbm2e_16Gb_3600.json $(DRAMSYS_PATH)/configs/memspec/.
214+
cp $(DRAM_CFG_PATH)/simconfig_hbm2e.json $(DRAMSYS_PATH)/configs/simconfig/.
215+
@if [ -f $(DRAMSYS_PATH)/configs/hbm2-example.json ]; then \
216+
mv $(DRAMSYS_PATH)/configs/hbm2-example.json \
217+
$(DRAMSYS_PATH)/configs/hbm2-example.json.ori; \
218+
fi
219+
cp $(DRAM_CFG_PATH)/HBM2E-3600.json $(DRAMSYS_PATH)/configs/hbm2-example.json
220+
cp $(DRAM_CFG_PATH)/am_ddr4.json $(DRAMSYS_PATH)/configs/addressmapping/.
221+
cp $(DRAM_CFG_PATH)/simconfig_ddr4.json $(DRAMSYS_PATH)/configs/simconfig/.
222+
@if [ -f $(DRAMSYS_PATH)/configs/ddr4-example.json ]; then \
223+
mv $(DRAMSYS_PATH)/configs/ddr4-example.json \
224+
$(DRAMSYS_PATH)/configs/ddr4-example.json.ori; \
225+
fi
226+
cp $(DRAM_CFG_PATH)/DDR4-2400.json $(DRAMSYS_PATH)/configs/ddr4-example.json
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228+
229+
dram-clean:
230+
if [ -d "$(DRAMSYS_PATH)/build" ]; then \
231+
rm -rf $(DRAMSYS_PATH)/build; \
232+
fi
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234+
# To ensure the dramsys is downloaded, only need to call at first time
235+
dram-init:
236+
make -C ${DRAMSYS_DIR} -j8 dramsys CXX=$(CXX) CC=$(CC)
198237

199238
############
200239
# Modelsim #

‎hardware/tb/dram_config/DDR4-2400.json‎

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@@ -0,0 +1,15 @@
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{
2+
"simulation": {
3+
"addressmapping": "am_ddr4.json",
4+
"mcconfig": "fr_fcfs.json",
5+
"memspec": "JEDEC_4Gb_DDR4-2400_8bit_A.json",
6+
"simconfig": "simconfig_ddr4.json",
7+
"simulationid": "ddr4",
8+
"tracesetup": [
9+
{
10+
"clkMhz": 1200,
11+
"name": "example.stl"
12+
}
13+
]
14+
}
15+
}

‎hardware/tb/dram_config/HBM2E-3600.json‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
{
2+
"simulation": {
3+
"addressmapping": "am_hbm2e_16Gb_pc_brc.json",
4+
"mcconfig": "mc_hbm2e_fr_fcfs_grp.json",
5+
"memspec": "ms_hbm2e_16Gb_3600.json",
6+
"simconfig": "simconfig_hbm2e.json",
7+
"simulationid": "hbm2e",
8+
"tracesetup": [
9+
{
10+
"clkMhz": 1800,
11+
"name": "HBM2E.stl"
12+
}
13+
]
14+
}
15+
}

‎hardware/tb/dram_config/am_ddr4.json‎

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{
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"addressmapping": {
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"BYTE_BIT": [
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0,
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1,
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2
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],
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"COLUMN_BIT": [
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],
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"BANK_BIT": [
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],
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"BANKGROUP_BIT":[
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],
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"ROW_BIT": [
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]
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}
47+
}

‎hardware/tb/dram_config/am_hbm2e_16Gb_pc_brc.json‎

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@@ -0,0 +1,47 @@
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{
2+
"addressmapping": {
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"BYTE_BIT": [
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0,
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1,
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2
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],
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"COLUMN_BIT": [
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],
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"PSEUDOCHANNEL_BIT":[
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5
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],
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"BANK_BIT": [
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],
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"BANKGROUP_BIT":[
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],
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"ROW_BIT": [
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]
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}
47+
}

‎hardware/tb/dram_config/mc_hbm2e_fr_fcfs_grp.json‎

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@@ -0,0 +1,20 @@
1+
{
2+
"mcconfig": {
3+
"PagePolicy": "Open",
4+
"Scheduler": "FrFcfsGrp",
5+
"SchedulerBuffer": "Bankwise",
6+
"RequestBufferSize": 128,
7+
"CmdMux": "Oldest",
8+
"RespQueue": "Fifo",
9+
"RefreshPolicy": "AllBank",
10+
"RefreshMaxPostponed": 8,
11+
"RefreshMaxPulledin": 8,
12+
"PowerDownPolicy": "NoPowerDown",
13+
"Arbiter": "Simple",
14+
"PhyDelayFw": 8,
15+
"PhyDelayBw": 9,
16+
"ThinkDelayFw": 12,
17+
"ThinkDelayBW": 12,
18+
"MaxActiveTransactions": 128
19+
}
20+
}

‎hardware/tb/dram_config/ms_hbm2e_16Gb_3600.json‎

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1+
{
2+
"memspec": {
3+
"memarchitecturespec": {
4+
"burstLength": 4,
5+
"dataRate": 2,
6+
"nbrOfBankGroups": 8,
7+
"nbrOfBanks": 32,
8+
"nbrOfColumns": 128,
9+
"nbrOfPseudoChannels": 2,
10+
"nbrOfRows": 32768,
11+
"width": 64,
12+
"nbrOfDevices": 1,
13+
"nbrOfChannels": 1
14+
},
15+
"memoryId": "Test MemPool-TeraPool with HBM2 upto 3600bps (16Gb, Single Channel)",
16+
"memoryType": "HBM2",
17+
"memtimingspec": {
18+
"CCDL": 4,
19+
"CCDS": 2,
20+
"CKE": 8,
21+
"DQSCK": 2,
22+
"FAW": 9,
23+
"PL": 2,
24+
"RAS": 30,
25+
"RC": 45,
26+
"RCDRD": 16,
27+
"RCDWR": 12,
28+
"REFI": 3900,
29+
"REFISB": 122,
30+
"RFC": 260,
31+
"RFCSB": 200,
32+
"RL": 41,
33+
"RP": 15,
34+
"RRDL": 2.22,
35+
"RRDS": 2.22,
36+
"RREFD": 8,
37+
"RTP": 4,
38+
"RTW": 18,
39+
"WL": 8,
40+
"WR": 41,
41+
"WTRL": 6,
42+
"WTRS": 4,
43+
"XP": 10,
44+
"XS": 270,
45+
"clkMhz": 1800
46+
}
47+
}
48+
}

‎hardware/tb/dram_config/simconfig_ddr4.json‎

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@@ -0,0 +1,15 @@
1+
{
2+
"simconfig": {
3+
"AddressOffset": 0,
4+
"CheckTLM2Protocol": false,
5+
"DatabaseRecording": true,
6+
"Debug": false,
7+
"EnableWindowing": false,
8+
"PowerAnalysis": false,
9+
"SimulationName": "ddr4",
10+
"SimulationProgressBar": true,
11+
"StoreMode": "Store",
12+
"UseMalloc": false,
13+
"WindowSize": 1000
14+
}
15+
}

‎hardware/tb/dram_config/simconfig_hbm2e.json‎

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{
2+
"simconfig": {
3+
"AddressOffset": 0,
4+
"CheckTLM2Protocol": false,
5+
"DatabaseRecording": true,
6+
"Debug": false,
7+
"EnableWindowing": true,
8+
"PowerAnalysis": false,
9+
"SimulationName": "hbm2e",
10+
"SimulationProgressBar": true,
11+
"StoreMode": "Store",
12+
"UseMalloc": false,
13+
"WindowSize": 300
14+
}
15+
}

‎hardware/tb/tb_cachepool.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ module tb_cachepool;
3030
import axi_pkg::xbar_cfg_t;
3131
import axi_pkg::xbar_rule_32_t;
3232

33-
localparam ClockPeriod = 2.0ns;
33+
localparam ClockPeriod = 1.0ns;
3434
localparam TA = 0.1ns;
3535
localparam TT = 0.4ns;
3636

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