`vlseg2e16.v` ignores active mask bit 5 and leaves lane 5 undisturbed

[KnightGOKU]

Describe the bug

Under matched VLEN = 4096 on both Spike and Ara, Ara can retire a masked vlseg2e16.v but fail to apply an active mask bit at lane 5.

The reduced testcase is:

vsetivli x0, 6, e16, m1

li      t0, 0x1111
vmv.v.x v13, t0
li      t0, 0x2222
vmv.v.x v14, t0

la      t0, mask_data
vlm.v   v0, (t0)              # mask_data = 0x20, only lane 5 active

la      t0, seg_data
vlseg2e16.v v13, (t0), v0.t

with:

• vl = 6
• only mask bit 5 active
• destination v13 preinitialized to 0x1111
• destination v14 preinitialized to 0x2222
• lane 5 source data equal to (0x1005, 0x2005)

Architecturally, lane 5 is active and should be loaded. Inactive lanes may remain undisturbed. This is not a trap issue. Both implementations retire the instruction successfully. The divergence is in the architectural vector result.

Expected behavior

Spike updates lane 5 because mask bit 5 is active:

mem 0x0000000080022828 0x0000000000001005
mem 0x0000000080022830 0x0000000000002005
mem 0x0000000080022840 0x0000000000000000   # exit code

This corresponds to:

• v13[5] = 0x1005
• v14[5] = 0x2005

Observed behavior

Ara retires the testcase successfully, but leaves lane 5 undisturbed:

mem 0x0000000080022828 0x0000000000001111
mem 0x0000000080022830 0x0000000000002222
mem 0x0000000080022840 0x0000000000000000   # exit code

Ara log:

Core Test *** SUCCESS *** (tohost = 0)

So Ara behaves as if mask bit 5 were inactive, even though it is the only active bit in v0.

To Reproduce

Build:

riscv64-unknown-elf-gcc -nostdlib -static \
  -march=rv64imfdcv_zicsr_zifencei_zfh \
  -mabi=lp64d \
  -T /home/ara_audit_repros/common.ld \
  -o /home/ara_audit_repros/b15_masked_vlseg2e16_lane5_vl6.elf \
  /home/ara_audit_repros/b15_masked_vlseg2e16_lane5_vl6.S

Run Spike:

/home/projects/projects/riscv-isa-sim/install/bin/spike \
  -p1 \
  --isa=RV64IMAFDCV_ZICSR_ZIFENCEI_ZFH_ZVL4096B \
  --log-commits \
  /home/ara_audit_repros/b15_masked_vlseg2e16_lane5_vl6.elf \
  > b15_masked_vlseg2e16_lane5_vl6.spike.log 2>&1

Run Ara:

/home/projects/projects/ara/hardware/build-rvfi9/verilator/Vara_tb_verilator \
  -l ram,/home/ara_audit_repros/b15_masked_vlseg2e16_lane5_vl6.elf,elf \
  > b15_masked_vlseg2e16_lane5_vl6.ara.log 2>&1

program.zip