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cva6rt: add configuration using the HPDCache
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Lines changed: 202 additions & 2 deletions

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‎Bender.yml‎

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@@ -115,6 +115,10 @@ sources:
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files:
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- core/include/cv64a6_rt_config_pkg.sv
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- target: cv64a6_rt_hpdcache
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files:
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- core/include/cv64a6_rt_hpdcache_config_pkg.sv
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# General config infrastructure
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- core/include/riscv_pkg.sv
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- core/include/ariane_pkg.sv
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- core/cva6_accel_first_pass_decoder_stub.sv
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# CLIC controller
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- target: any(cv64a6_imafdchsclic_sv39, cv64a6_imafdchsclic_sv39_hpdcache_wb, cv64a6_imafdchsclic_sv39_wb, cv64a6_imafdchxhclic_sv39_wb, cv64a6_imafdchxhclic_sv39_hpdcache_wb, cv64a6_rt)
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- target: any(cv64a6_imafdchsclic_sv39, cv64a6_imafdchsclic_sv39_hpdcache_wb, cv64a6_imafdchsclic_sv39_wb, cv64a6_imafdchxhclic_sv39_wb, cv64a6_imafdchxhclic_sv39_hpdcache_wb, cv64a6_rt, cv64a6_rt_hpdcache)
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files:
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- core/cva6_clic_controller.sv
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# MMU
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- target: any(cv64a6_imafdcv_sv39, cv64a6_imafdc_sv39, cv64a6_imafdc_sv39_wb, cv64a6_imafdch_sv39, cv64a6_imafdc_sv39_hpdcache, cv64a6_imafdc_sv39_hpdcache_wb, cv64a6_imafdch_sv39_wb, cv64a6_imafdchsclic_sv39, cv64a6_imafdchsclic_sv39_wb, cv64a6_imafdchsclic_sv39_hpdcache_wb, cv64a6_imafdchxhclic_sv39_wb, cv64a6_imafdchxhclic_sv39_hpdcache_wb, cv64a6_splus, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32, cv64a6_rt)
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- target: any(cv64a6_imafdcv_sv39, cv64a6_imafdc_sv39, cv64a6_imafdc_sv39_wb, cv64a6_imafdch_sv39, cv64a6_imafdc_sv39_hpdcache, cv64a6_imafdc_sv39_hpdcache_wb, cv64a6_imafdch_sv39_wb, cv64a6_imafdchsclic_sv39, cv64a6_imafdchsclic_sv39_wb, cv64a6_imafdchsclic_sv39_hpdcache_wb, cv64a6_imafdchxhclic_sv39_wb, cv64a6_imafdchxhclic_sv39_hpdcache_wb, cv64a6_splus, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32, cv64a6_rt, cv64a6_rt_hpdcache)
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files:
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- core/cva6_mmu/cva6_tlb.sv
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- core/cva6_mmu/cva6_shared_tlb.sv

‎core/include/cv64a6_rt_hpdcache_config_pkg.sv‎

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// Copyright 2021 Thales DIS design services SAS
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//
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// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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// You may obtain a copy of the License at https://solderpad.org/licenses/
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//
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// Original Author: Enrico Zelioli <ezelioli@iis.ee.ethz.ch> - ETH Zurich
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package cva6_config_pkg;
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localparam CVA6ConfigXlen = 64;
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localparam CVA6ConfigRVF = 1;
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localparam CVA6ConfigRVD = 1;
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localparam CVA6ConfigF16En = 0;
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localparam CVA6ConfigF16AltEn = 0;
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localparam CVA6ConfigF8En = 0;
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localparam CVA6ConfigFVecEn = 0;
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localparam CVA6ConfigCvxifEn = 0;
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localparam CVA6ConfigCExtEn = 1;
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localparam CVA6ConfigZcbExtEn = 1;
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localparam CVA6ConfigZcmpExtEn = 0;
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localparam CVA6ConfigAExtEn = 1;
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localparam CVA6ConfigHExtEn = 1;
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localparam CVA6ConfigBExtEn = 0;
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localparam CVA6ConfigVExtEn = 0;
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localparam CVA6ConfigRVZiCond = 1;
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localparam CVA6ConfigSclicExtEn = 1;
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localparam CVA6ConfigXhclicExtEn = 1;
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localparam CVA6ConfigAxiIdWidth = 4;
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localparam CVA6ConfigAxiAddrWidth = 48;
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localparam CVA6ConfigAxiDataWidth = 64;
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localparam CVA6ConfigFetchUserEn = 0;
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localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen;
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localparam CVA6ConfigDataUserEn = 0;
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localparam CVA6ConfigDataUserWidth = 1;
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localparam CVA6ConfigIcacheByteSize = 16384;
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localparam CVA6ConfigIcacheSetAssoc = 4;
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localparam CVA6ConfigIcacheLineWidth = 128;
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localparam CVA6ConfigDcacheByteSize = 32768;
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localparam CVA6ConfigDcacheSetAssoc = 8;
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localparam CVA6ConfigDcacheLineWidth = 128;
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localparam CVA6ConfigICacheSpmAddrBase = 56'h01A0_0000;
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localparam CVA6ConfigDCacheSpmAddrBase = 56'h0180_0000;
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// do not flush Dcache for EVERY fence - dramatic performance impact
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// use RVZiCbom to synchronize caches with DMA devices instead
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// CAUTION - a configuration with CVA6ConfigDcacheFlushOnFence might be required for different SoCs, e.g., cache-coherent SMP configurations
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localparam CVA6ConfigDcacheFlushOnFence = 1'b0;
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localparam CVA6ConfigDcacheFlushOnFenceI = 1'b1;
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localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0;
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localparam CVA6ConfigDcacheIdWidth = 1; // Must be >= $clog2(CVA6Cfg.NrLoadBufEntries)
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localparam CVA6ConfigMemTidWidth = CVA6ConfigAxiIdWidth;
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localparam CVA6ConfigWtDcacheWbufDepth = 7;
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localparam CVA6ConfigNrScoreboardEntries = 8;
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localparam CVA6ConfigNrLoadPipeRegs = 1;
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localparam CVA6ConfigNrStorePipeRegs = 0;
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localparam CVA6ConfigNrLoadBufEntries = 2;
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localparam CVA6ConfigRASDepth = 2;
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localparam CVA6ConfigBTBEntries = 32;
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localparam CVA6ConfigBHTEntries = 128;
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localparam CVA6ConfigTvalEn = 1;
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localparam CVA6ConfigNrPMPEntries = 8;
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localparam CVA6ConfigPerfCounterEn = 1;
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localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE_WB;
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localparam CVA6ConfigMmuPresent = 1;
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localparam CVA6ConfigRvfiTrace = 1;
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localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
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XLEN: unsigned'(CVA6ConfigXlen),
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VLEN: unsigned'(64),
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FpgaEn: bit'(0), // for Xilinx and Altera
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FpgaAlteraEn: bit'(0), // for Altera (only)
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TechnoCut: bit'(0),
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SuperscalarEn: bit'(0),
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ALUBypass: bit'(0),
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NrCommitPorts: unsigned'(2),
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AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
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AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
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AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
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AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
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MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
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NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
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RVF: bit'(CVA6ConfigRVF),
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RVD: bit'(CVA6ConfigRVD),
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XF16: bit'(CVA6ConfigF16En),
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XF16ALT: bit'(CVA6ConfigF16AltEn),
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XF8: bit'(CVA6ConfigF8En),
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RVA: bit'(CVA6ConfigAExtEn),
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RVB: bit'(CVA6ConfigBExtEn),
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ZKN: bit'(0),
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RVV: bit'(CVA6ConfigVExtEn),
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RVC: bit'(CVA6ConfigCExtEn),
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RVH: bit'(CVA6ConfigHExtEn),
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RVZCB: bit'(CVA6ConfigZcbExtEn),
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RVZCMT: bit'(0),
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RVZCMP: bit'(CVA6ConfigZcmpExtEn),
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RVSCLIC: bit'(CVA6ConfigSclicExtEn),
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RVXHCLIC: bit'(CVA6ConfigXhclicExtEn),
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XFVec: bit'(CVA6ConfigFVecEn),
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CvxifEn: bit'(CVA6ConfigCvxifEn),
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CoproType: config_pkg::COPRO_NONE,
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RVZiCond: bit'(CVA6ConfigRVZiCond),
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RVZiCbom: bit'(0),
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RVZicntr: bit'(1),
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RVZihpm: bit'(1),
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NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries),
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PerfCounterEn: bit'(CVA6ConfigPerfCounterEn),
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MmuPresent: bit'(CVA6ConfigMmuPresent),
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RVS: bit'(1),
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RVU: bit'(1),
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SoftwareInterruptEn: bit'(1),
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HaltAddress: 64'h800,
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ExceptionAddress: 64'h808,
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RASDepth: unsigned'(CVA6ConfigRASDepth),
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BTBEntries: unsigned'(CVA6ConfigBTBEntries),
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BPType: config_pkg::BHT,
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BHTEntries: unsigned'(CVA6ConfigBHTEntries),
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BHTHist: unsigned'(3),
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DmBaseAddress: 64'h0,
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TvalEn: bit'(CVA6ConfigTvalEn),
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DirectVecOnly: bit'(0),
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NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
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PMPCfgRstVal: {64{64'h0}},
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PMPAddrRstVal: {64{64'h0}},
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PMPEntryReadOnly: 64'd0,
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PMPNapotEn: bit'(1),
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NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
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CLICNumInterruptSrc: unsigned'(256),
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NrNonIdempotentRules: unsigned'(2),
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NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
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NonIdempotentLength: 1024'({64'b0, 64'b0}),
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NrExecuteRegionRules: unsigned'(4),
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ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'(CVA6ConfigICacheSpmAddrBase), 64'h1_0000, 64'h0}),
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ExecuteRegionLength: 1024'({64'h40000000, 64'(CVA6ConfigIcacheByteSize), 64'h10000, 64'h1000}),
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NrCachedRegionRules: unsigned'(1),
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CachedRegionAddrBase: 1024'({64'h8000_0000}),
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CachedRegionLength: 1024'({64'h40000000}),
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MaxOutstandingStores: unsigned'(7),
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DebugEn: bit'(1),
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SDTRIG: bit'(0),
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Mcontrol6: bit'(0),
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Icount: bit'(0),
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Etrigger: bit'(0),
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Itrigger: bit'(0),
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AxiBurstWriteEn: bit'(0),
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IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize),
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IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc),
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IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth),
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ICacheSpmAddrBase: 56'(CVA6ConfigICacheSpmAddrBase),
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ICacheSpmLength: 56'(CVA6ConfigIcacheByteSize),
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DCacheSpmAddrBase: 56'(CVA6ConfigDCacheSpmAddrBase),
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DCacheSpmLength: 56'(CVA6ConfigDcacheByteSize),
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DCacheType: CVA6ConfigDcacheType,
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DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
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DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
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DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
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DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence),
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DcacheFlushOnFenceI: unsigned'(CVA6ConfigDcacheFlushOnFenceI),
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DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush),
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DataUserEn: unsigned'(CVA6ConfigDataUserEn),
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WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
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FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
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FetchUserEn: unsigned'(CVA6ConfigFetchUserEn),
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InstrTlbEntries: int'(16),
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DataTlbEntries: int'(64),
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TlbColoring: bit'(1),
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NumTlbColors: int'(16),
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LockableTlbWays: int'(8),
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UseSharedTlb: bit'(0),
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SvnapotEn: bit'(0),
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SharedTlbDepth: int'(64),
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NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
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NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
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DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
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};
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endpackage
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