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arichardsontariqkurd-repo
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RVY encodings matching latest 0.9.8.3 draft
Matching the latest version of https://riscv.github.io/riscv-cheri/ Co-authored-by: Tariq Kurd <tariq.kurd@codasip.com>
1 parent ec5d992 commit 0645a51

14 files changed

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‎arg_lut.csv‎

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"rd_n2", 11, 7
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"rd_n0", 11, 7
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"rs1_n0", 11, 7
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"rs2_n0", 24, 20
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"c_rs2_n0", 6, 2
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"c_rs1_n0", 11, 7
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"c_rs2", 6, 2
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"p_rd_p", 11, 8
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"p_rs1_p", 19, 16
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"p_rs2_p", 24, 21
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"ybndswimm9", 28, 20

‎csrs.csv‎

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0x257, "vsireg6"
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0x25C, "vstopei"
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0x280, "vsatp"
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0x480, "utidc"
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0x580, "stidc"
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0x780, "mtidc"
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0xA80, "vstidc"
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0x600, "hstatus"
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0x602, "hedeleg"
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0x603, "hideleg"
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0x3ed, "pmpaddr61"
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0x3ee, "pmpaddr62"
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0x3ef, "pmpaddr63"
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0x416, "ddc"
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0x747, "mseccfg"
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0x7a0, "tselect"
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0x7a1, "tdata1"
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0x7b1, "dpc"
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0x7b2, "dscratch0"
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0x7b3, "dscratch1"
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0x7ba, "drootcsel"
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0x7bc, "dddc"
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0x7bd, "drootc"
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0xB00, "mcycle"
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0xB02, "minstret"
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0xB03, "mhpmcounter3"

‎extensions/unratified/rv32_y‎

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# 32-bit YHIR pseudo-op
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$pseudo_op rv_y::srliy yhir rd rs1 31..27=0 26..20=32 14..12=5 6..2=0x1E 1..0=3

‎extensions/unratified/rv32_y_c‎

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# When the base ISA is RV32Y, the Zcf instructions are remapped loads/stores of capabilities:
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# c.ly: repurposes c.flw
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# c.sy: repurposes c.fsw
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# c.lysp: repurposes c.flwsp
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# c.sysp: repurposes c.fswsp
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c.ly_rv32 rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=3
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c.sy_rv32 rs1_p rs2_p c_uimm8hi c_uimm8lo 1..0=0 15..13=7
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c.lysp_rv32 rd_n0 c_uimm9sphi c_uimm9splo 1..0=2 15..13=3
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c.sysp_rv32 c_rs2 c_uimm9sp_s 1..0=2 15..13=7

‎extensions/unratified/rv64_y‎

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# 64-bit YHIR pseudo-op
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$pseudo_op rv_y::srliy yhir rd rs1 31..27=0 26..20=64 14..12=5 6..2=0x1E 1..0=3

‎extensions/unratified/rv64_y_c‎

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# When the base ISA is RV64Y, the Zcd instructions are remapped loads/stores of capabilities:
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# c.ly: repurposes c.fld
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# c.sy: repurposes c.fsd
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# c.lysp: repurposes c.fldsp
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# c.sysp: repurposes c.fsdsp
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c.ly_rv64 rd_p rs1_p c_uimm9lo c_uimm9hi 1..0=0 15..13=1
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c.sy_rv64 rs1_p rs2_p c_uimm9hi c_uimm9lo 1..0=0 15..13=5
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c.lysp_rv64 rd_n0 c_uimm10sphi c_uimm10splo 1..0=2 15..13=1
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c.sysp_rv64 c_rs2 c_uimm10sp_s 1..0=2 15..13=5

‎extensions/unratified/rv64_y_zba‎

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# Operand Types: rd YLEN, rs1 XLEN, rs2 YLEN (0b101)
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ysh4add rd rs1 rs2 31..25=0b0011_101 14..12=0 6..2=0x1E 1..0=3
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ysh1add.uw rd rs1 rs2 31..25=0b0100_101 14..12=0 6..2=0x1E 1..0=3
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ysh2add.uw rd rs1 rs2 31..25=0b0101_101 14..12=0 6..2=0x1E 1..0=3
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ysh3add.uw rd rs1 rs2 31..25=0b0110_101 14..12=0 6..2=0x1E 1..0=3
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ysh4add.uw rd rs1 rs2 31..25=0b0111_101 14..12=0 6..2=0x1E 1..0=3

‎extensions/unratified/rv_a_y‎

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lr.y rd rs1 aq rl 31..27=0b00010 24..20=0 14..12=3 6..2=0x1E 1..0=3
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sc.y rd rs1 rs2 aq rl 31..27=0b00011 14..12=3 6..2=0x1E 1..0=3
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amoswap.y rd rs1 rs2 aq rl 31..27=0b00001 14..12=3 6..2=0x1E 1..0=3

‎extensions/unratified/rv_y‎

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# R-Type Instructions
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#
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# The lower 3 bits of funct7 [27:25] are a bitmask indicating YLEN (capability) operands:
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# bit 25: rd (0 = XLEN, 1 = YLEN)
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# bit 26: rs1 (0 = XLEN, 1 = YLEN)
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# bit 27: rs2 (0 = XLEN, 1 = YLEN)
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# Operand Types: rd YLEN, rs1 XLEN, rs2 XLEN (0b001)
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packy rd rs1 rs2 31..25=0b0000_001 14..12=0 6..2=0x1E 1..0=3
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$pseudo_op rv_y::packy yhiw rd rs1 rs2 31..25=0b0000_001 14..12=0 6..2=0x1E 1..0=3
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# Operand Types: rd YLEN, rs1 YLEN, rs2 XLEN (0b011)
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yadd rd rs1 rs2_n0 31..25=0b0000_011 14..12=0 6..2=0x1E 1..0=3
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ymv rd rs1 31..25=0b0000_011 24..20=0 14..12=0 6..2=0x1E 1..0=3
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yaddrw rd rs1 rs2 31..25=0b0001_011 14..12=0 6..2=0x1E 1..0=3
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ypermc rd rs1 rs2 31..25=0b0010_011 14..12=0 6..2=0x1E 1..0=3
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ybndsw rd rs1 rs2 31..25=0b0011_011 14..12=0 6..2=0x1E 1..0=3
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ybndsrw rd rs1 rs2 31..25=0b0100_011 14..12=0 6..2=0x1E 1..0=3
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# Operand Types: rd XLEN, rs1 YLEN, rs2 YLEN (0b110)
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yeq rd rs1 rs2 31..25=0b0000_110 14..12=0 6..2=0x1E 1..0=3
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yss rd rs1 rs2 31..25=0b0001_110 14..12=0 6..2=0x1E 1..0=3
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# Operand Types: rd YLEN, rs1 YLEN, rs2 YLEN (0b111)
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ysunseal rd rs1 rs2 31..25=0b0000_111 14..12=0 6..2=0x1E 1..0=3
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ybld rd rs1 rs2 31..25=0b0001_111 14..12=0 6..2=0x1E 1..0=3
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#rs2 is in the format, but must be zero for now (non-zero will be yseal)
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ysentry rd rs1 24..20=0 31..25=0b0010_111 14..12=0 6..2=0x1E 1..0=3
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# 2-OP Instructions (encoded as R-type with using 1111 in the upper bits of funct7 and rs2=funct5)
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# Operand Types: rd XLEN, rs1 XLEN, rs2 N/A (0b000)
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yamask rd rs1 31..25=0b1111_000 24..20=0 14..12=0 6..2=0x1E 1..0=3
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# Operand Types: rd XLEN, rs1 YLEN, rs2 N/A (0b010)
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ybaser rd rs1 31..25=0b1111_010 24..20=0 14..12=0 6..2=0x1E 1..0=3
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ypermr rd rs1 31..25=0b1111_010 24..20=1 14..12=0 6..2=0x1E 1..0=3
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ytopr rd rs1 31..25=0b1111_010 24..20=2 14..12=0 6..2=0x1E 1..0=3
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ylenr rd rs1 31..25=0b1111_010 24..20=3 14..12=0 6..2=0x1E 1..0=3
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ytagr rd rs1 31..25=0b1111_010 24..20=4 14..12=0 6..2=0x1E 1..0=3
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ytyper rd rs1 31..25=0b1111_010 24..20=5 14..12=0 6..2=0x1E 1..0=3
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# I-Type / S-Type Instructions
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yaddi rd rs1 imm12 14..12=4 6..2=0x1E 1..0=3
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ly rd rs1 imm12 14..12=1 6..2=0x1E 1..0=3
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sy imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x1E 1..0=3
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# MISC Instructions
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ybndswi rd rs1 ybndswimm9 31..29=0b111 14..12=5 6..2=0x1E 1..0=3
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srliy rd rs1 shamtq 31..27=0b00000 14..12=5 6..2=0x1E 1..0=3

‎extensions/unratified/rv_y_c‎

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# When the base ISA is RVY, c.mv is remapped to c.ymv to copy YLEN-wide values
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c.ymv rd_n0 c_rs2_n0 1..0=2 15..13=4 12=0

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