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mb/system76/ptl: Add Adder Pro 6 (addp6)
Change-Id: Ic41be2f407aa9d8fe81b74e19a656e265c201f5d Signed-off-by: Tim Crawford <tcrawford@system76.com>
1 parent ed65ab2 commit 43c420e

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Lines changed: 366 additions & 0 deletions

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‎src/mainboard/system76/ptl/Kconfig‎

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@@ -26,6 +26,11 @@ config BOARD_SYSTEM76_PTL_COMMON
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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config BOARD_SYSTEM76_ADDP6
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select BOARD_SYSTEM76_PTL_COMMON
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select DRIVERS_GFX_NVIDIA
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select EC_SYSTEM76_EC_DGPU
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2934
config BOARD_SYSTEM76_LEMP14
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select BOARD_SYSTEM76_PTL_COMMON
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select DRIVERS_I2C_TAS5825M
@@ -46,19 +51,23 @@ config MAINBOARD_DIR
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default "system76/ptl"
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4853
config VARIANT_DIR
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default "addp6" if BOARD_SYSTEM76_ADDP6
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default "lemp14" if BOARD_SYSTEM76_LEMP14 || BOARD_SYSTEM76_LEMP14_B
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5157
config OVERRIDE_DEVICETREE
5258
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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5460
config MAINBOARD_PART_NUMBER
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default "addp6" if BOARD_SYSTEM76_ADDP6
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default "lemp14" if BOARD_SYSTEM76_LEMP14
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default "lemp14-b" if BOARD_SYSTEM76_LEMP14_B
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5865
config MAINBOARD_SMBIOS_PRODUCT_NAME
66+
default "Adder Pro" if BOARD_SYSTEM76_ADDP6
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default "Lemur Pro" if BOARD_SYSTEM76_LEMP14 || BOARD_SYSTEM76_LEMP14_B
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6169
config MAINBOARD_VERSION
70+
default "addp6" if BOARD_SYSTEM76_ADDP6
6271
default "lemp14" if BOARD_SYSTEM76_LEMP14
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default "lemp14-b" if BOARD_SYSTEM76_LEMP14_B
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‎src/mainboard/system76/ptl/Kconfig.name‎

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@@ -1,5 +1,8 @@
11
## SPDX-License-Identifier: GPL-2.0-only
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config BOARD_SYSTEM76_ADDP6
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bool "addp6"
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36
config BOARD_SYSTEM76_LEMP14
47
bool "lemp14"
58

‎src/mainboard/system76/ptl/variants/addp6/board.fmd‎

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@@ -0,0 +1,12 @@
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FLASH 32M {
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SI_DESC 16K
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SI_ME 9176K
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SI_BIOS@16M 16M {
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RW_MRC_CACHE 64K
6+
SMMSTORE(PRESERVE) 512K
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WP_RO {
8+
FMAP 4K
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COREBOOT(CBFS)
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}
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}
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}

‎src/mainboard/system76/ptl/variants/addp6/board_info.txt‎

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Board name: addp6
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Release year: 2026

‎src/mainboard/system76/ptl/variants/addp6/gpio.c‎

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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootstate.h>
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#include <mainboard/gpio.h>
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#include <soc/gpio.h>
6+
7+
static const struct pad_config gpio_table[] = {
8+
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC
9+
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, DN_20K, DEEP, NF1), // ESPI_CLK_EC
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET#
15+
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PAD_NC(GPP_A08, NONE), // SOC_SML_SCL (NC)
17+
PAD_NC(GPP_A09, NONE), // SOC_SML_SDA (NC)
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PAD_NC(GPP_A10, NONE),
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PAD_NC(GPP_A11, NONE), // WLAN_RST#
20+
PAD_NC(GPP_A12, NONE), // WLAN_WAKEUP# (NC)
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PAD_NC(GPP_A13, NONE), // NVVDD_TALERT#
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PAD_NC(GPP_A15, NONE), // EPD_ON_GCD_IN
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PAD_NC(GPP_A16, NONE), // PCH_BT_EN
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PAD_NC(GPP_A17, NONE), // WIFI_RF_EN
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PAD_NC(GPP_B00, NONE), // SOC_SMLINK_I2C_SCL
27+
PAD_NC(GPP_B01, NONE), // SOC_SMLINK_I2C_SDA
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PAD_NC(GPP_B02, NONE),
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PAD_NC(GPP_B03, NONE),
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PAD_NC(GPP_B04, NONE), // CPU_ME_WE / Flash Descriptor Security Override strap
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PAD_NC(GPP_B05, NONE), // PS8461_SW_PCH (NC)
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PAD_NC(GPP_B06, NONE),
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PAD_NC(GPP_B07, NONE),
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PAD_NC(GPP_B08, NONE),
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//PAD_NC(GPP_B09, NONE), // M2_SSD2_RST#
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PAD_NC(GPP_B10, NONE), // CPU_HDMI_HPD
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PAD_NC(GPP_B11, NONE), // TCP2_HPD (CPU_TYPEC1_DP_HPD)
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PAD_NC(GPP_B12, NONE), // SLP_S0# (NC)
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PAD_NC(GPP_B13, NONE), // PLT_RST#
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PAD_NC(GPP_B14, NONE), // TCP3_HPD (CPU_TYPEC2_DP_HPD)
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PAD_CFG_GPI(GPP_B15, NONE), // USB_OC3# (10k P/U to 1.8VA)
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//PAD_NC(GPP_B16, NONE), // SSD1_PWR_EN
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PAD_NC(GPP_B17, NONE),
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PAD_NC(GPP_B18, NONE),
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PAD_NC(GPP_B19, NONE),
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PAD_NC(GPP_B20, NONE),
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PAD_NC(GPP_B21, NONE),
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PAD_NC(GPP_B22, NONE),
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PAD_NC(GPP_B23, NONE), // Reserved strap
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PAD_NC(GPP_B24, NONE),
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PAD_NC(GPP_B25, NONE),
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PAD_NC(GPP_C00, NONE), // SMB_CLK_DDR (NC)
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PAD_NC(GPP_C01, NONE), // SMB_DATA_DDR (NC)
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PAD_NC(GPP_C02, NONE), // TLS confidentiality strap
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PAD_NC(GPP_C03, NONE), // SOC_LAN_SML0_SCL (NC)
57+
PAD_NC(GPP_C04, NONE), // SOC_LAN_SML0_SDA (NC)
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PAD_NC(GPP_C05, NONE), // eSPI disable strap
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PAD_NC(GPP_C06, NONE), // SOC_SML1_SCL (NC)
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PAD_NC(GPP_C07, NONE), // SOC_SML1_SDA (NC)
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PAD_NC(GPP_C08, NONE),
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PAD_NC(GPP_C09, NONE),
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PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), // GPU_CLK1REQ#_N
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PAD_NC(GPP_C11, NONE),
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PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), // LAN_CLK3REQ#_N
66+
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), // WLAN_CLK4REQ#_N
67+
//PAD_NC(GPP_C14, NONE), // SSD1_CLK5REQ#_N
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PAD_NC(GPP_C15, NONE), // Reserved strap
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PAD_NC(GPP_C16, NONE),
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PAD_NC(GPP_C17, NONE),
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PAD_NC(GPP_C18, NONE),
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PAD_NC(GPP_C19, NONE),
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PAD_NC(GPP_C20, NONE),
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PAD_NC(GPP_C21, NONE),
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PAD_NC(GPP_C22, NONE),
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PAD_NC(GPP_C23, NONE),
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PAD_CFG_GPO(GPP_D00, 1, DEEP), // SB_BLON
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PAD_NC(GPP_D01, NONE), // FW_EN_PD (NC)
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PAD_NC(GPP_D02, NONE), // FW_EN_RETIMER (NC)
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PAD_NC(GPP_D03, NONE), // EC_SYS_PWROK (NC)
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PAD_NC(GPP_D04, NONE),
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PAD_NC(GPP_D05, NONE),
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PAD_NC(GPP_D06, NONE),
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PAD_NC(GPP_D07, NONE),
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PAD_NC(GPP_D08, NONE),
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//PAD_NC(GPP_D09, NONE), // DGPU_RST#
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PAD_NC(GPP_D10, NONE), // HDA_BITCLK
89+
PAD_NC(GPP_D11, NONE), // HDA_SYNC
90+
PAD_NC(GPP_D12, NONE), // HDA_SDOUT
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PAD_NC(GPP_D13, NONE), // HDA_SDIN0
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PAD_NC(GPP_D14, NONE),
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PAD_NC(GPP_D15, NONE), // CNVI_WAKE#
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PAD_NC(GPP_D16, NONE), // HDA_RST#
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PAD_NC(GPP_D17, NONE),
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//PAD_NC(GPP_D18, NONE), // SSD2_CLK6REQ#_N
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PAD_CFG_GPI(GPP_D19, NONE, PLTRST), // 10k P/U to 1.8VS
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PAD_NC(GPP_D20, NONE),
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PAD_NC(GPP_D21, NONE),
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PAD_CFG_GPI(GPP_D22, NONE, PLTRST), // 1k P/U to 1.8VA
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PAD_CFG_GPI(GPP_D23, NONE, PLTRST), // 1k P/U to 1.8VA
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PAD_NC(GPP_D24, NONE),
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PAD_NC(GPP_D25, NONE),
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105+
PAD_NC(GPP_E01, NONE), // TPM_PIRQ#
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PAD_NC(GPP_E02, NONE), // VRALERT# (NC)
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//PAD_NC(GPP_E03, NONE), // M2_SSD1_RST#
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PAD_NC(GPP_E05, NONE),
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PAD_NC(GPP_E06, NONE), // JTAG ODT strap
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PAD_NC(GPP_E07, NONE),
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//PAD_NC(GPP_E08, NONE), // SSD2_PWR_EN
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PAD_CFG_GPI(GPP_E09, NONE), // USB_OC0# (10k P/U to 1.8VA)
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PAD_NC(GPP_E10, NONE), // "QUALIFIED BY DFXTESTMODE" strap
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//PAD_NC(GPP_E11, NONE), // BOARD_ID1
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PAD_NC(GPP_E12, NONE),
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PAD_NC(GPP_E13, NONE),
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//PAD_NC(GPP_E14, NONE), // BOARD_ID2
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//PAD_NC(GPP_E15, NONE), // BOARD_ID3
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PAD_NC(GPP_E16, NONE),
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//PAD_NC(GPP_E17, NONE), // BOARD_ID4
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PAD_NC(GPP_E18, NONE),
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PAD_NC(GPP_E19, NONE), // PCH_GPIO_LANRTD3
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PAD_NC(GPP_E20, NONE),
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PAD_NC(GPP_E21, NONE), // SOC_SMLINK_I2C_INT (NC)
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PAD_NC(GPP_E22, NONE),
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PAD_NC(GPP_F00, NONE), // CNVI_BRI_DT
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PAD_NC(GPP_F01, NONE), // CNVI_BRI_RSP
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PAD_NC(GPP_F02, NONE), // CNVI_RGI_DT / M.2 CNVi mode strap
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PAD_NC(GPP_F03, NONE), // CNVI_RGI_RSP
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PAD_NC(GPP_F04, NONE), // CNVI_RST#
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PAD_NC(GPP_F05, NONE), // CNVI_CLKREQ
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PAD_NC(GPP_F06, NONE), // CNVI_GNSS_PA_BLANKING
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PAD_NC(GPP_F07, NONE),
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PAD_NC(GPP_F08, NONE),
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PAD_CFG_GPI(GPP_F09, NONE, PLTRST), // TPM_DET: 0=None, 1=Present
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PAD_NC(GPP_F10, NONE),
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PAD_NC(GPP_F11, NONE),
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), // I2C_SCL_TP
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), // I2C_SDA_TP
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//PAD_NC(GPP_F14, NONE), // DGPU_PWR_EN
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PAD_NC(GPP_F15, NONE), // GPIO4_GC6_NVVDD_EN
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PAD_NC(GPP_F16, NONE), // CCD_WP#
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PAD_NC(GPP_F17, NONE), // GC6_FB_EN_PCH
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PAD_CFG_GPI_APIC_LOW(GPP_F18, NONE, DEEP), // TP_ATTN#
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PAD_NC(GPP_F19, NONE), // Reserved strap
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//PAD_NC(GPP_F20, NONE), // DGPU_PWRGD
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PAD_NC(GPP_F22, NONE),
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PAD_NC(GPP_F23, NONE),
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PAD_NC(GPP_H00, NONE), // eSPI Flash Sharing Mode strap: 0=CAFS, 1=TAFS
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PAD_NC(GPP_H01, NONE), // Flash Descriptor Recovery strap
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PAD_NC(GPP_H02, NONE), // Reserved strap
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PAD_NC(GPP_H03, NONE),
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PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
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PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
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PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), // CPU_PD_I2C_SDA
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PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), // CPU_PD_I2C_SCL
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//PAD_NC(GPP_H08, NONE), // UART_RX
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//PAD_NC(GPP_H09, NONE), // UART_TX
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PAD_NC(GPP_H10, NONE),
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PAD_NC(GPP_H11, NONE),
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PAD_NC(GPP_H13, NONE), // CPU_C10_GATE# (NC)
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PAD_NC(GPP_H14, NONE),
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PAD_NC(GPP_H15, NONE),
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PAD_NC(GPP_H16, NONE),
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PAD_NC(GPP_H17, NONE),
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PAD_NC(GPP_H19, NONE),
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PAD_NC(GPP_H20, NONE),
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PAD_NC(GPP_H21, NONE), // CPU_REDRIVER_I2C_SDA (NC)
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PAD_NC(GPP_H22, NONE), // CPU_REDRIVER_I2C_SCL (NC)
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PAD_NC(GPP_S00, NONE),
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PAD_NC(GPP_S01, NONE),
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PAD_NC(GPP_S02, NONE),
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PAD_NC(GPP_S03, NONE),
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PAD_NC(GPP_S04, NONE), // M.2_BT_PCMCLK (NC)
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PAD_NC(GPP_S05, NONE), // M.2_BT_PCMFRM_CRF_RST_N (NC)
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PAD_NC(GPP_S06, NONE), // M.2_BT_PCMOUT_CLKREQ0 (NC)
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PAD_NC(GPP_S07, NONE), // M.2_BT_PCMIN (NC)
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PAD_NC(GPP_V00, NONE), // PM_BATLOW#
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PAD_NC(GPP_V01, NONE), // SOC_AC_PRESENT
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PAD_NC(GPP_V02, NONE), // PCH_LAN_WAKE# (NC)
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PAD_NC(GPP_V03, NONE), // SOC_PWR_BTN#
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PAD_NC(GPP_V04, NONE), // SUSB#_PCH
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PAD_NC(GPP_V05, NONE), // SUSC#_PCH
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PAD_NC(GPP_V06, NONE), // SLP_A# (NC)
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PAD_NC(GPP_V07, NONE), // SUS_CLK
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PAD_NC(GPP_V08, NONE), // SLP_WLAN# (NC)
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PAD_NC(GPP_V09, NONE),
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PAD_NC(GPP_V10, NONE), // LANPHYPC
193+
PAD_NC(GPP_V11, NONE), // LAN_CTRL_PWREN (NC)
194+
PAD_NC(GPP_V12, NONE), // PCH_WAKEUP#
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PAD_NC(GPP_V16, NONE), // VCCST_EN
196+
PAD_NC(GPP_V17, NONE),
197+
};
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void mainboard_configure_gpios(void)
200+
{
201+
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
202+
}
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static const struct pad_config nvme_pwr_seq2[] = {
205+
PAD_CFG_GPO(GPP_B16, 1, PLTRST), // SSD1_PWR_EN
206+
PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), // SSD1_CLK5REQ#_N
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PAD_CFG_GPO(GPP_E08, 1, PLTRST), // SSD2_PWR_EN
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PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // SSD2_CLK6REQ#_N
209+
};
210+
211+
static void nvme_enable_power(void *unused)
212+
{
213+
gpio_configure_pads(nvme_pwr_seq2, ARRAY_SIZE(nvme_pwr_seq2));
214+
}
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BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, nvme_enable_power, NULL);
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static const struct pad_config nvme_pwr_seq3[] = {
219+
PAD_CFG_GPO(GPP_E03, 1, PLTRST), // M2_SSD1_RST#
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PAD_CFG_GPO(GPP_B09, 1, PLTRST), // M2_SSD2_RST#
221+
};
222+
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static void nvme_deassert_perst(void *unused)
224+
{
225+
gpio_configure_pads(nvme_pwr_seq3, ARRAY_SIZE(nvme_pwr_seq3));
226+
}
227+
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BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, nvme_deassert_perst, NULL);

‎src/mainboard/system76/ptl/variants/addp6/gpio_early.c‎

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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <mainboard/gpio.h>
4+
#include <soc/gpio.h>
5+
6+
static const struct pad_config early_gpio_table[] = {
7+
// Model detection
8+
PAD_CFG_GPI(GPP_E11, NONE, PLTRST), // BOARD_ID1
9+
PAD_CFG_GPI(GPP_E14, NONE, PLTRST), // BOARD_ID2
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PAD_CFG_GPI(GPP_E15, NONE, PLTRST), // BOARD_ID3
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PAD_CFG_GPI(GPP_E17, NONE, PLTRST), // BOARD_ID4
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13+
// Debug
14+
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
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PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
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// SSD1
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PAD_CFG_GPO(GPP_B16, 0, PLTRST), // SSD1_PWR_EN
19+
PAD_CFG_GPO(GPP_E03, 0, PLTRST), // M2_SSD1_RST#
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PAD_CFG_GPI(GPP_C14, NONE, DEEP), // SSD1_CLK5REQ#_N
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// SSD2
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PAD_CFG_GPO(GPP_E08, 0, PLTRST), // SSD2_PWR_EN
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PAD_CFG_GPO(GPP_B09, 0, PLTRST), // M2_SSD2_RST#
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PAD_CFG_GPI(GPP_D18, NONE, DEEP), // SSD2_CLK6REQ#_N
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27+
// dGPU
28+
PAD_CFG_GPO(GPP_F14, 0, DEEP), // DGPU_PWR_EN
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PAD_CFG_GPI(GPP_F20, NONE, DEEP), // DGPU_PWRGD
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PAD_CFG_GPO(GPP_D09, 0, DEEP), // DGPU_RST#
31+
32+
};
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void mainboard_configure_early_gpios(void)
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{
36+
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
37+
}

‎src/mainboard/system76/ptl/variants/addp6/hda_verb.c‎

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/* SPDX-License-Identifier: GPL-2.0-only */
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3+
#include <device/azalia_device.h>
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5+
static const u32 realtek_alc255_verbs[] = {
6+
AZALIA_SUBVENDOR(0, 0x15580000), // TODO
7+
AZALIA_RESET(1),
8+
AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
9+
AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_CFG_NC(0)),
10+
AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
11+
AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
12+
AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
13+
AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
14+
AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
15+
AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)),
16+
AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
17+
AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_CFG_NC(0)),
18+
};
19+
20+
const u32 pc_beep_verbs[] = {};
21+
22+
struct azalia_codec mainboard_azalia_codecs[] = {
23+
{
24+
.name = "Realtek ALC255",
25+
.vendor_id = 0x10ec0255,
26+
.subsystem_id = 0, // TODO
27+
.address = 0,
28+
.verbs = realtek_alc255_verbs,
29+
.verb_count = ARRAY_SIZE(realtek_alc255_verbs),
30+
}
31+
};
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AZALIA_ARRAY_SIZES;

‎src/mainboard/system76/ptl/variants/addp6/overridetree.cb‎

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# SPDX-License-Identifier: GPL-2.0-only
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chip soc/intel/pantherlake
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register "common_soc_config" = "{
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 80,
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.fall_time_ns = 110,
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}
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}"
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device domain 0 on
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#subsystemid 0x1558 0x000 inherit
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end
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end

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