diff --git a/src/mainboard/system76/ptl/Kconfig b/src/mainboard/system76/ptl/Kconfig index b0b1728fa4a..fa93a9701aa 100644 --- a/src/mainboard/system76/ptl/Kconfig +++ b/src/mainboard/system76/ptl/Kconfig @@ -26,6 +26,12 @@ config BOARD_SYSTEM76_PTL_COMMON select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP +config BOARD_SYSTEM76_ADDP6 + select BOARD_SYSTEM76_PTL_COMMON + select DRIVERS_GFX_NVIDIA + select EC_SYSTEM76_EC_DGPU + select EC_SYSTEM76_EC_OLED + config BOARD_SYSTEM76_LEMP14 select BOARD_SYSTEM76_PTL_COMMON select DRIVERS_I2C_TAS5825M @@ -46,19 +52,23 @@ config MAINBOARD_DIR default "system76/ptl" config VARIANT_DIR + default "addp6" if BOARD_SYSTEM76_ADDP6 default "lemp14" if BOARD_SYSTEM76_LEMP14 || BOARD_SYSTEM76_LEMP14_B config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_PART_NUMBER + default "addp6" if BOARD_SYSTEM76_ADDP6 default "lemp14" if BOARD_SYSTEM76_LEMP14 default "lemp14-b" if BOARD_SYSTEM76_LEMP14_B config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Adder Pro" if BOARD_SYSTEM76_ADDP6 default "Lemur Pro" if BOARD_SYSTEM76_LEMP14 || BOARD_SYSTEM76_LEMP14_B config MAINBOARD_VERSION + default "addp6" if BOARD_SYSTEM76_ADDP6 default "lemp14" if BOARD_SYSTEM76_LEMP14 default "lemp14-b" if BOARD_SYSTEM76_LEMP14_B diff --git a/src/mainboard/system76/ptl/Kconfig.name b/src/mainboard/system76/ptl/Kconfig.name index c598dde5353..495890bb17e 100644 --- a/src/mainboard/system76/ptl/Kconfig.name +++ b/src/mainboard/system76/ptl/Kconfig.name @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config BOARD_SYSTEM76_ADDP6 + bool "addp6" + config BOARD_SYSTEM76_LEMP14 bool "lemp14" diff --git a/src/mainboard/system76/ptl/acpi/mainboard.asl b/src/mainboard/system76/ptl/acpi/mainboard.asl index 92fefd20bb9..a9183188ebd 100644 --- a/src/mainboard/system76/ptl/acpi/mainboard.asl +++ b/src/mainboard/system76/ptl/acpi/mainboard.asl @@ -7,6 +7,9 @@ Scope (\_SB) { #include "sleep.asl" Scope (PCI0) { +#if !CONFIG(EC_SYSTEM76_EC_OLED) #include "backlight.asl" +#endif + /* TODO: Add NVIDIA include */ } } diff --git a/src/mainboard/system76/ptl/variants/addp6/board.fmd b/src/mainboard/system76/ptl/variants/addp6/board.fmd new file mode 100644 index 00000000000..aec4da22f06 --- /dev/null +++ b/src/mainboard/system76/ptl/variants/addp6/board.fmd @@ -0,0 +1,12 @@ +FLASH 32M { + SI_DESC 16K + SI_ME 9176K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 512K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/system76/ptl/variants/addp6/board_info.txt b/src/mainboard/system76/ptl/variants/addp6/board_info.txt new file mode 100644 index 00000000000..7497f432d8d --- /dev/null +++ b/src/mainboard/system76/ptl/variants/addp6/board_info.txt @@ -0,0 +1,2 @@ +Board name: addp6 +Release year: 2026 diff --git a/src/mainboard/system76/ptl/variants/addp6/gpio.c b/src/mainboard/system76/ptl/variants/addp6/gpio.c new file mode 100644 index 00000000000..2a8b6158eca --- /dev/null +++ b/src/mainboard/system76/ptl/variants/addp6/gpio.c @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET# + + PAD_NC(GPP_A08, NONE), // SOC_SML_SCL (NC) + PAD_NC(GPP_A09, NONE), // SOC_SML_SDA (NC) + PAD_NC(GPP_A10, NONE), + PAD_CFG_GPO(GPP_A11, 1, DEEP), // WLAN_RST# + PAD_NC(GPP_A12, NONE), // WLAN_WAKEUP# (NC) + PAD_NC(GPP_A13, NONE), // NVVDD_TALERT# (NC?) + PAD_NC(GPP_A15, NONE), // EPD_ON_GCD_IN + PAD_NC(GPP_A16, NONE), // PCH_BT_EN (NC) + PAD_CFG_GPO(GPP_A17, 1, NONE), // WIFI_RF_EN + + PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), // SOC_SMLINK_I2C_SCL + PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), // SOC_SMLINK_I2C_SDA + PAD_NC(GPP_B02, NONE), + PAD_NC(GPP_B03, NONE), + PAD_CFG_GPI(GPP_B04, NONE), // CPU_ME_WE / Flash Descriptor Security Override strap + PAD_NC(GPP_B05, NONE), // PS8461_SW_PCH (NC) + PAD_NC(GPP_B06, NONE), + PAD_NC(GPP_B07, NONE), + PAD_NC(GPP_B08, NONE), + //PAD_NC(GPP_B09, NONE), // M2_SSD2_RST# + PAD_NC(GPP_B10, NONE), // CPU_HDMI_HPD (NC?) + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // TCP2_HPD (CPU_TYPEC1_DP_HPD) + PAD_NC(GPP_B12, NONE), // SLP_S0# (NC) + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), // TCP3_HPD (CPU_TYPEC2_DP_HPD) + PAD_CFG_GPI(GPP_B15, NONE), // USB_OC3# (10k P/U to 1.8VA) + //PAD_NC(GPP_B16, NONE), // SSD1_PWR_EN + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_NC(GPP_B23, NONE), // Reserved strap + PAD_NC(GPP_B24, NONE), + PAD_NC(GPP_B25, NONE), + + PAD_NC(GPP_C00, NONE), // SMB_CLK_DDR (NC) + PAD_NC(GPP_C01, NONE), // SMB_DATA_DDR (NC) + PAD_NC(GPP_C02, NONE), // TLS confidentiality strap + PAD_NC(GPP_C03, NONE), // SOC_LAN_SML0_SCL (NC) + PAD_NC(GPP_C04, NONE), // SOC_LAN_SML0_SDA (NC) + PAD_NC(GPP_C05, NONE), // eSPI disable strap + PAD_NC(GPP_C06, NONE), // SOC_SML1_SCL (NC) + PAD_NC(GPP_C07, NONE), // SOC_SML1_SDA (NC) + PAD_NC(GPP_C08, NONE), + PAD_NC(GPP_C09, NONE), + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), // GPU_CLK1REQ#_N + PAD_NC(GPP_C11, NONE), + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), // LAN_CLK3REQ#_N + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), // WLAN_CLK4REQ#_N + //PAD_NC(GPP_C14, NONE), // SSD1_CLK5REQ#_N + PAD_NC(GPP_C15, NONE), // Reserved strap + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + PAD_CFG_GPO(GPP_D00, 1, DEEP), // SB_BLON + PAD_NC(GPP_D01, NONE), // FW_EN_PD (NC) + PAD_NC(GPP_D02, NONE), // FW_EN_RETIMER (NC) + PAD_NC(GPP_D03, NONE), // EC_SYS_PWROK (NC) + PAD_NC(GPP_D04, NONE), + PAD_NC(GPP_D05, NONE), + PAD_NC(GPP_D06, NONE), + PAD_NC(GPP_D07, NONE), + PAD_NC(GPP_D08, NONE), + //PAD_NC(GPP_D09, NONE), // DGPU_RST# + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), // HDA_SDOUT + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), // HDA_SDIN0 + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), // CNVI_WAKE# + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), // HDA_RST# + PAD_NC(GPP_D17, NONE), + //PAD_NC(GPP_D18, NONE), // SSD2_CLK6REQ#_N + PAD_CFG_GPI(GPP_D19, NONE, PLTRST), // 10k P/U to 1.8VS + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_CFG_GPI(GPP_D22, NONE, PLTRST), // 1k P/U to 1.8VA + PAD_CFG_GPI(GPP_D23, NONE, PLTRST), // 1k P/U to 1.8VA + PAD_NC(GPP_D24, NONE), + PAD_NC(GPP_D25, NONE), + + PAD_CFG_GPI_SCI_LOW(GPP_E01, NONE, DEEP, EDGE_SINGLE), // TPM_PIRQ# + PAD_NC(GPP_E02, NONE), // VRALERT# (NC) + //PAD_NC(GPP_E03, NONE), // M2_SSD1_RST# + PAD_NC(GPP_E05, NONE), + PAD_NC(GPP_E06, NONE), // JTAG ODT strap + PAD_NC(GPP_E07, NONE), + //PAD_NC(GPP_E08, NONE), // SSD2_PWR_EN + PAD_CFG_GPI(GPP_E09, NONE), // USB_OC0# (10k P/U to 1.8VA) + PAD_NC(GPP_E10, NONE), // "QUALIFIED BY DFXTESTMODE" strap + //PAD_NC(GPP_E11, NONE), // BOARD_ID1 + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + //PAD_NC(GPP_E14, NONE), // BOARD_ID2 + //PAD_NC(GPP_E15, NONE), // BOARD_ID3 + PAD_NC(GPP_E16, NONE), + //PAD_NC(GPP_E17, NONE), // BOARD_ID4 + PAD_NC(GPP_E18, NONE), + PAD_NC(GPP_E19, NONE), // PCH_GPIO_LANRTD3 (NC) + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), // SOC_SMLINK_I2C_INT (NC) + PAD_NC(GPP_E22, NONE), + + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F01, NONE, UP_20K, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT / M.2 CNVi mode strap + PAD_CFG_NF(GPP_F03, NONE, UP_20K, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), // CNVI_RST# + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), // CNVI_CLKREQ + PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_NC(GPP_F07, NONE), + PAD_NC(GPP_F08, NONE), + PAD_CFG_GPI(GPP_F09, NONE, PLTRST), // TPM_DET: 0=None, 1=Present + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), // I2C_SCL_TP + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), // I2C_SDA_TP + //PAD_NC(GPP_F14, NONE), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_F15, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN (10k P/U to 1V8_AON) + PAD_CFG_GPO(GPP_F16, 0, DEEP), // CCD_WP# + PAD_CFG_GPI(GPP_F17, NONE), // GC6_FB_EN_PCH + PAD_CFG_GPI_APIC_LOW(GPP_F18, NONE, DEEP), // TP_ATTN# + PAD_NC(GPP_F19, NONE), // Reserved strap + //PAD_NC(GPP_F20, NONE), // DGPU_PWRGD + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + PAD_NC(GPP_H00, NONE), // eSPI Flash Sharing Mode strap: 0=CAFS, 1=TAFS + PAD_NC(GPP_H01, NONE), // Flash Descriptor Recovery strap + PAD_NC(GPP_H02, NONE), // Reserved strap + PAD_NC(GPP_H03, NONE), + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), // CNVI_MFUART2_TXD + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), // CPU_PD_I2C_SDA + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), // CPU_PD_I2C_SCL + //PAD_NC(GPP_H08, NONE), // UART_RX + //PAD_NC(GPP_H09, NONE), // UART_TX + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H13, NONE), // CPU_C10_GATE# (NC) + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), // CPU_REDRIVER_I2C_SDA (NC) + PAD_NC(GPP_H22, NONE), // CPU_REDRIVER_I2C_SCL (NC) + + PAD_NC(GPP_S00, NONE), + PAD_NC(GPP_S01, NONE), + PAD_NC(GPP_S02, NONE), + PAD_NC(GPP_S03, NONE), + PAD_NC(GPP_S04, NONE), // M.2_BT_PCMCLK (NC) + PAD_NC(GPP_S05, NONE), // M.2_BT_PCMFRM_CRF_RST_N (NC) + PAD_NC(GPP_S06, NONE), // M.2_BT_PCMOUT_CLKREQ0 (NC) + PAD_NC(GPP_S07, NONE), // M.2_BT_PCMIN (NC) + + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // PM_BATLOW# + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // SOC_AC_PRESENT + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // PCH_LAN_WAKE# (NC?) + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // SOC_PWR_BTN# + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SUSB#_PCH + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), // SUSC#_PCH + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), // SLP_A# (NC?) + PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), // SUS_CLK + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), // SLP_WLAN# (NC?) + PAD_NC(GPP_V09, NONE), + PAD_NC(GPP_V10, NONE), + PAD_NC(GPP_V11, NONE), + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), // PCH_WAKEUP# + PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), // VCCST_EN + PAD_NC(GPP_V17, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static const struct pad_config nvme_pwr_seq2[] = { + PAD_CFG_GPO(GPP_B16, 1, PLTRST), // SSD1_PWR_EN + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), // SSD1_CLK5REQ#_N + PAD_CFG_GPO(GPP_E08, 1, PLTRST), // SSD2_PWR_EN + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // SSD2_CLK6REQ#_N +}; + +static void nvme_enable_power(void *unused) +{ + gpio_configure_pads(nvme_pwr_seq2, ARRAY_SIZE(nvme_pwr_seq2)); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, nvme_enable_power, NULL); + +static const struct pad_config nvme_pwr_seq3[] = { + PAD_CFG_GPO(GPP_E03, 1, PLTRST), // M2_SSD1_RST# + PAD_CFG_GPO(GPP_B09, 1, PLTRST), // M2_SSD2_RST# +}; + +static void nvme_deassert_perst(void *unused) +{ + gpio_configure_pads(nvme_pwr_seq3, ARRAY_SIZE(nvme_pwr_seq3)); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, nvme_deassert_perst, NULL); diff --git a/src/mainboard/system76/ptl/variants/addp6/gpio_early.c b/src/mainboard/system76/ptl/variants/addp6/gpio_early.c new file mode 100644 index 00000000000..0c49d9739e9 --- /dev/null +++ b/src/mainboard/system76/ptl/variants/addp6/gpio_early.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + // Model detection + PAD_CFG_GPI(GPP_E11, NONE, PLTRST), // BOARD_ID1 + PAD_CFG_GPI(GPP_E14, NONE, PLTRST), // BOARD_ID2 + PAD_CFG_GPI(GPP_E15, NONE, PLTRST), // BOARD_ID3 + PAD_CFG_GPI(GPP_E17, NONE, PLTRST), // BOARD_ID4 + + // Debug + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX + + // SSD1 + PAD_CFG_GPO(GPP_B16, 0, PLTRST), // SSD1_PWR_EN + PAD_CFG_GPO(GPP_E03, 0, PLTRST), // M2_SSD1_RST# + PAD_CFG_GPI(GPP_C14, NONE, DEEP), // SSD1_CLK5REQ#_N + + // SSD2 + PAD_CFG_GPO(GPP_E08, 0, PLTRST), // SSD2_PWR_EN + PAD_CFG_GPO(GPP_B09, 0, PLTRST), // M2_SSD2_RST# + PAD_CFG_GPI(GPP_D18, NONE, DEEP), // SSD2_CLK6REQ#_N + + // dGPU + PAD_CFG_GPO(GPP_F14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_F20, NONE, DEEP), // DGPU_PWRGD + PAD_CFG_GPO(GPP_D09, 0, DEEP), // DGPU_RST# + +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/ptl/variants/addp6/hda_verb.c b/src/mainboard/system76/ptl/variants/addp6/hda_verb.c new file mode 100644 index 00000000000..192d2169028 --- /dev/null +++ b/src/mainboard/system76/ptl/variants/addp6/hda_verb.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const u32 realtek_alc255_verbs[] = { + AZALIA_SUBVENDOR(0, 0x1558f551), + AZALIA_RESET(0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( // 0x90a60130 + AZALIA_INTEGRATED, + AZALIA_INTERNAL | AZALIA_GEOLOCATION_NA, + AZALIA_MIC_IN, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, + 0 + )), + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( // 0x90170110 + AZALIA_INTEGRATED, + AZALIA_INTERNAL | AZALIA_GEOLOCATION_NA, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, + 0 + )), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), // NC + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x41e79b45), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( // 0x04211020 + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 2, + 0 + )), + + 0x02050038, 0x02047981, + 0x02050038, 0x02047981, + 0x05750003, 0x057486a6, + 0x02050034, 0x02048204, + 0x0205001b, 0x02040a0b, + 0x02050046, 0x02040004, + 0x02050008, 0x02046a0e, + 0x02050040, 0x02041800, + 0x02050037, 0x02044a06, + 0x0205004c, 0x02044803, +}; + +const u32 pc_beep_verbs[] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC255", + .vendor_id = 0x10ec0255, + .subsystem_id = 0x1558f551, + .address = 0, + .verbs = realtek_alc255_verbs, + .verb_count = ARRAY_SIZE(realtek_alc255_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/ptl/variants/addp6/overridetree.cb b/src/mainboard/system76/ptl/variants/addp6/overridetree.cb new file mode 100644 index 00000000000..f14e483d64a --- /dev/null +++ b/src/mainboard/system76/ptl/variants/addp6/overridetree.cb @@ -0,0 +1,215 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/pantherlake + register "common_soc_config" = "{ + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + } + }" + + # TODO + #register "power_limits_config[]" = "{ + # .tdp_pl1_override = , + # .tdp_pl2_override = , + #}" + + device domain 0 on + subsystemid 0x1558 0xf551 inherit + + device ref igpu on + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + chip drivers/gfx/generic + register "device_count" = "3" + # DDIA: eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = ""panel"" + # TCP2: USB3.2 Gen2 + DP1.4 (J_TYPEC1) + register "device[1].name" = ""DD01"" + register "device[1].use_pld" = "true" + register "device[1].pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 1))" + # TCP3: USB3.2 Gen2 + DP1.4 (J_TYPEC2) + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 2))" + # HDMI connected through dGPU + device generic 0 on end + end + end + device ref tcss_xhci on + register "tcss_ports" = "{ + [2] = TCSS_PORT_DEFAULT(OC_SKIP), + [3] = TCSS_PORT_DEFAULT(OC_SKIP), + }" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""J_TYPEC1"" + register "type" = "UPC_TYPE_USB3_A" + device ref tcss_usb3_port2 + end + chip drivers/usb/acpi + register "desc" = ""J_TYPEC2"" + register "type" = "UPC_TYPE_USB3_A" + device ref tcss_usb3_port3 + end + end + end + end + device ref heci_1 on end # XXX: Needed? + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* USB Type-A */ + [1] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC2 */ + [2] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC1 */ + [4] = USB2_PORT_MID(OC_SKIP), /* USB Type-A*/ + [6] = USB2_PORT_MID(OC_SKIP), /* Camera */ + [7] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A */ + }" + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3.2 Gen 1 (ARJ_USB1)"" + register "type" = "UPC_TYPE_A" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3.2 Gen2 + DP1.4 (J_TYPEC2)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3.2 Gen2 + DP1.4 (J_TYPEC1)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3.2 Gen 1 (RJ_USB1)"" + register "type" = "UPC_TYPE_A" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3.2 Gen 1 (ARJ_USB1)"" + register "type" = "UPC_TYPE_USB3_A" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3.2 Gen 1 (RJ_USB1)"" + register "type" = "UPC_TYPE_USB3_A" + device ref usb3_port2 on end + end + end + end + end + device ref i2c3 on end # XXX: USB-PD? + device ref eheci1 on end # XXX: Needed? + device ref i2c5 on + # Touchpad + register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref pcie_rp1 on + # SSD2 + register "pcie_rp[PCIE_RP(1)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E08)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)" + register "srcclk_pin" = "6" + device generic 0 on end + end + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" + end + device ref pcie_rp7 on + # LAN + register "pcie_rp[PCIE_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + # No RTD3 + end + device ref pcie_rp8 on + # WLAN + register "pcie_rp[PCIE_RP(8)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "4" + device generic 0 on end + end + chip drivers/wifi/generic + use usb2_port8 as bluetooth_companion + device pci 00.0 on end + end + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device ref pcie_rp9 on + # SSD1 + register "pcie_rp[PCIE_RP(9)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)" + register "srcclk_pin" = "5" + device generic 0 on end + end + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + device ref pcie_rp11 on + # DGPU + register "pcie_rp[PCIE_RP(11)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + end + end +end diff --git a/src/mainboard/system76/ptl/variants/addp6/romstage.c b/src/mainboard/system76/ptl/variants/addp6/romstage.c new file mode 100644 index 00000000000..e010bf9c94e --- /dev/null +++ b/src/mainboard/system76/ptl/variants/addp6/romstage.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .rcomp = { .resistor = 100, }, + .ect = true, + .user_bd = BOARD_TYPE_ULT_ULX, + .lp_ddr_dq_dqs_re_training = 1, + .ddr_config = { .dq_pins_interleaved = false, }, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50 }, + [1] = { .addr_dimm[0] = 0x52 }, + }, + }; + const bool half_populated = false; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +}