Original issue is #16.
The uvm reg adapter needs to support not only AXI4-Lite but also AXI4.
To support AXI4, following changes are needed.
- Set
bust size and bust length fields
- Set
id field
- Shift write and read data according to
rw.n_bits and lower address bits
configuration object may be needed to get bus width
Original issue is #16.
The uvm reg adapter needs to support not only AXI4-Lite but also AXI4.
To support AXI4, following changes are needed.
bust sizeandbust lengthfieldsidfieldrw.n_bitsandlower address bitsconfigurationobject may be needed to getbus width