style: apply cargo fmt fixes for memory addr range check

Apply nightly rustfmt formatting to all files modified by the
fix(air): enforce word_addr is a valid u32 change.

Changes:
- Reflow import groups to fit within nightly rustfmt's line-length rules
- Reflow doc comments and inline comments to match nightly wrap width
- Collapse single-expression let bindings that fit on one line
- Lowercase hex literal 0xFFFF -> 0xffff (rustfmt convention)
- Flatten multi-line arithmetic chains that fit within the width limit

Author: amathxbt

air/src/constraints/chiplets/memory.rs

@@ -39,8 +39,8 @@ use crate::{
     trace::{
         CHIPLETS_OFFSET,
         chiplets::{
-            MEMORY_ADDR_HI_COL_IDX, MEMORY_ADDR_LO_COL_IDX, MEMORY_CLK_COL_IDX,
-            MEMORY_CTX_COL_IDX, MEMORY_D_INV_COL_IDX, MEMORY_D0_COL_IDX, MEMORY_D1_COL_IDX,
+            MEMORY_ADDR_HI_COL_IDX, MEMORY_ADDR_LO_COL_IDX, MEMORY_CLK_COL_IDX, MEMORY_CTX_COL_IDX,
+            MEMORY_D_INV_COL_IDX, MEMORY_D0_COL_IDX, MEMORY_D1_COL_IDX,
             MEMORY_FLAG_SAME_CONTEXT_AND_WORD, MEMORY_IDX0_COL_IDX, MEMORY_IDX1_COL_IDX,
             MEMORY_IS_READ_COL_IDX, MEMORY_IS_WORD_ACCESS_COL_IDX, MEMORY_V_COL_RANGE,
             MEMORY_WORD_COL_IDX,
@@ -231,8 +231,8 @@ pub fn enforce_memory_constraints_all_rows<AB>(
     //
     // Fix: commit to the 16-bit limbs of word_addr (addr_lo, addr_hi) and add:
     //   1. Reconstruction: word_addr = addr_hi * 2^16 + addr_lo
-    //   2. Range checks for addr_lo and addr_hi go through the existing range-check bus
-    //      (submitted from the prover's append_range_checks).
+    //   2. Range checks for addr_lo and addr_hi go through the existing range-check bus (submitted
+    //      from the prover's append_range_checks).
     //   3. Overflow guard: 4 * addr_hi < 2^16, ensuring word_addr * 4 + 3 < 2^32.
     enforce_addr_range_check::<AB>(builder, memory_flag, &cols);
 }
@@ -683,11 +683,11 @@ pub fn flag_next_row_first_memory<E: PrimeCharacteristicRing>(
 /// `addr_hi = word_addr >> 16` and add three constraints:
 ///
 /// 1. **Reconstruction**: `word_addr = addr_hi * 2^16 + addr_lo`
-/// 2. **Range checks**: `addr_lo ∈ [0, 2^16)` and `addr_hi ∈ [0, 2^16)` — submitted via
-///    the existing range-check bus in [`Memory::append_range_checks`].
-/// 3. **Overflow guard**: `4 * addr_hi < 2^16`, ensuring `word_addr * 4 + 3 < 2^32`,
-///    i.e. every element-level address derived from this word address is a valid u32.
-///    (This is also submitted as a range check: `4 * addr_hi` must be in `[0, 2^16)`.)
+/// 2. **Range checks**: `addr_lo ∈ [0, 2^16)` and `addr_hi ∈ [0, 2^16)` — submitted via the
+///    existing range-check bus in [`Memory::append_range_checks`].
+/// 3. **Overflow guard**: `4 * addr_hi < 2^16`, ensuring `word_addr * 4 + 3 < 2^32`, i.e. every
+///    element-level address derived from this word address is a valid u32. (This is also submitted
+///    as a range check: `4 * addr_hi` must be in `[0, 2^16)`.)
 ///
 /// ## Why no new global columns are needed
 ///

air/src/constraints/range/bus.rs

@@ -90,13 +90,11 @@ where
     // Additional address range-check lookups: addr_lo, addr_hi, and 4*addr_hi.
     // These close the soundness gap where the delta-based range checks only bound
     // differences between consecutive addresses, not absolute address values.
-    let mv_addr_lo: AB::ExprEF =
-        alpha.into() + local.chiplets[MEMORY_ADDR_LO_IDX].clone().into();
-    let mv_addr_hi: AB::ExprEF =
-        alpha.into() + local.chiplets[MEMORY_ADDR_HI_IDX].clone().into();
+    let mv_addr_lo: AB::ExprEF = alpha.into() + local.chiplets[MEMORY_ADDR_LO_IDX].clone().into();
+    let mv_addr_hi: AB::ExprEF = alpha.into() + local.chiplets[MEMORY_ADDR_HI_IDX].clone().into();
     // 4 * addr_hi: enforces word_addr * 4 + 3 < 2^32 (overflow guard).
-    let mv_addr_hi_x4: AB::ExprEF = alpha.into()
-        + AB::Expr::from_u16(4) * local.chiplets[MEMORY_ADDR_HI_IDX].clone().into();
+    let mv_addr_hi_x4: AB::ExprEF =
+        alpha.into() + AB::Expr::from_u16(4) * local.chiplets[MEMORY_ADDR_HI_IDX].clone().into();
 
     // Stack lookups: sv0-sv3 = alpha + decoder helper columns
     let sv0: AB::ExprEF = alpha.into() + local.decoder[STACK_LOOKUP_BASE].clone().into();
@@ -108,11 +106,8 @@ where
     let range_check: AB::ExprEF = alpha.into() + local.range[RANGE_V_COL_IDX].clone().into();
 
     // Combined lookup denominators
-    let memory_lookups = mv0.clone()
-        * mv1.clone()
-        * mv_addr_lo.clone()
-        * mv_addr_hi.clone()
-        * mv_addr_hi_x4.clone();
+    let memory_lookups =
+        mv0.clone() * mv1.clone() * mv_addr_lo.clone() * mv_addr_hi.clone() * mv_addr_hi_x4.clone();
     let stack_lookups = sv0.clone() * sv1.clone() * sv2.clone() * sv3.clone();
     let lookups = range_check.clone() * stack_lookups.clone() * memory_lookups.clone();
 
@@ -162,11 +157,7 @@ where
         * mv1.clone()
         * mv_addr_lo.clone()
         * mv_addr_hi_x4.clone();
-    let m_addr_hi_x4_term = mflag_rc_stack
-        * mv0
-        * mv1
-        * mv_addr_lo
-        * mv_addr_hi;
+    let m_addr_hi_x4_term = mflag_rc_stack * mv0 * mv1 * mv_addr_lo * mv_addr_hi;
 
     // Main constraint: b_next * lookups = b * lookups + rc_term - s_terms - m_terms
     builder.tagged(TAG_RANGE_BUS_BASE, RANGE_BUS_NAME, |builder| {

processor/src/trace/chiplets/memory/mod.rs

@@ -4,10 +4,10 @@ use core::fmt::Debug;
 use miden_air::trace::{
     RowIndex,
     chiplets::memory::{
-        ADDR_HI_COL_IDX, ADDR_LO_COL_IDX, CLK_COL_IDX, CTX_COL_IDX, D_INV_COL_IDX,
-        D0_COL_IDX, D1_COL_IDX, FLAG_SAME_CONTEXT_AND_WORD, IDX0_COL_IDX, IDX1_COL_IDX,
-        IS_READ_COL_IDX, IS_WORD_ACCESS_COL_IDX, MEMORY_ACCESS_ELEMENT, MEMORY_ACCESS_WORD,
-        MEMORY_READ, MEMORY_WRITE, V_COL_RANGE, WORD_COL_IDX,
+        ADDR_HI_COL_IDX, ADDR_LO_COL_IDX, CLK_COL_IDX, CTX_COL_IDX, D_INV_COL_IDX, D0_COL_IDX,
+        D1_COL_IDX, FLAG_SAME_CONTEXT_AND_WORD, IDX0_COL_IDX, IDX1_COL_IDX, IS_READ_COL_IDX,
+        IS_WORD_ACCESS_COL_IDX, MEMORY_ACCESS_ELEMENT, MEMORY_ACCESS_WORD, MEMORY_READ,
+        MEMORY_WRITE, V_COL_RANGE, WORD_COL_IDX,
     },
 };
 

processor/src/trace/chiplets/memory/tests.rs

@@ -3,9 +3,9 @@ use alloc::vec::Vec;
 use miden_air::trace::{
     RowIndex,
     chiplets::memory::{
-        ADDR_HI_COL_IDX, ADDR_LO_COL_IDX, FLAG_SAME_CONTEXT_AND_WORD, IDX0_COL_IDX,
-        IDX1_COL_IDX, IS_READ_COL_IDX, IS_WORD_ACCESS_COL_IDX, MEMORY_ACCESS_ELEMENT,
-        MEMORY_ACCESS_WORD, MEMORY_READ, MEMORY_WRITE, TRACE_WIDTH as MEMORY_TRACE_WIDTH,
+        ADDR_HI_COL_IDX, ADDR_LO_COL_IDX, FLAG_SAME_CONTEXT_AND_WORD, IDX0_COL_IDX, IDX1_COL_IDX,
+        IS_READ_COL_IDX, IS_WORD_ACCESS_COL_IDX, MEMORY_ACCESS_ELEMENT, MEMORY_ACCESS_WORD,
+        MEMORY_READ, MEMORY_WRITE, TRACE_WIDTH as MEMORY_TRACE_WIDTH,
     },
 };
 use miden_core::{ONE, WORD_SIZE, Word, ZERO, assert_matches, field::Field};
@@ -580,7 +580,7 @@ fn build_trace_row(
     // Populate address limb columns matching what fill_trace() writes.
     // ADDR_LO = word_addr & 0xFFFF, ADDR_HI = word_addr >> 16.
     let word_addr_u32: u32 = word.as_canonical_u64().try_into().unwrap();
-    let addr_lo = u16::try_from(word_addr_u32 & 0xFFFF).unwrap();
+    let addr_lo = u16::try_from(word_addr_u32 & 0xffff).unwrap();
     let addr_hi = u16::try_from(word_addr_u32 >> 16).unwrap();
     row[ADDR_LO_COL_IDX] = Felt::new(addr_lo as u64);
     row[ADDR_HI_COL_IDX] = Felt::new(addr_hi as u64);