WIP: Libpayload x64 #7
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Clang does not recognize dead_code() as termination of execution. It
gives this message:
error: control reaches end of non-void function
[-Werror,-Wreturn-type]
This change adds an __attribute__((noreturn)) to ensure that clang
recognises that this function will terminate execution.
This change is more general solution to the problem that was addressed
in the specific at https://review.coreboot.org/c/coreboot/+/32798
Signed-off-by: Alan Green <[email protected]>
Change-Id: I5ba7189559aa01545d5bbe893bced400a3aaabbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32833
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Julius Werner <[email protected]>
This fixes the following changes, which made qualcomm Kconfig appear on all platforms: bd0b51c 7a3e46d Use proper Kconfig logic. Change-Id: I0195fd186ac39dd4258fe0781dd6d3d1b1d1679f Signed-off-by: Patrick Rudolph <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32805 Reviewed-by: Patrick Georgi <[email protected]> Reviewed-by: Julius Werner <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Set the system serial number from the VPD key "serial_number" and the mainboard serial number from the VPD key "mlb_serial_number". BUG=b:132970635 TEST=check serial number is set in SMBIOS based on VPD, and if there is no VPD key found then it is empty. Change-Id: Ia8f1486dcb1edc968b8eb1e6d989b10c05913aca Signed-off-by: Duncan Laurie <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32851 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Lijian Zhao <[email protected]> Reviewed-by: Furquan Shaikh <[email protected]>
Fill the DIMM serial number field for SMBIOS from the saved SPD
data that is returned by FSP.
BUG=b:132970635
TEST=This was tested on sarien to ensure that SMBIOS type 17
filled the serial number from the DIMM:
Handle 0x000B, DMI type 17, 40 bytes
Memory Device
Locator: DIMM-A
Serial Number: 41164beb
Change-Id: I85438bd1d581095ea3482dcf077a7f3389f1cd47
Signed-off-by: Duncan Laurie <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32853
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Lijian Zhao <[email protected]>
According to JEP106 from JEDEC, fix manufacture ID of Crucial, Super Talnet and Micron. Signed-off-by: Lijian Zhao <[email protected]> Change-Id: I10a268a7f3bde405b95bd3a16d5d121be623c7ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/32837 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: HAOUAS Elyes <[email protected]> Reviewed-by: Duncan Laurie <[email protected]> Reviewed-by: Patrick Rudolph <[email protected]>
The VPD field name is dock_passthrough, not dock_passthru. Fix it. (I assume there is no length limit) BUG=b:132689337 TEST=check that the feature can now be controlled by the associated enterprise policy Change-Id: Icc2b070313fde74447279cd6ccaa4e3eb6d119ee Signed-off-by: Simon Glass <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32839 Reviewed-by: Duncan Laurie <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
With CB:32726 ("lib/timestamp: Make timestamp_sync_cache_to_cbmem() in
postcar") timestamps are synced from cache to cbmem in postcar as
well. For postcar, the cache lives in BSS just like ramstage. This
change updates TIMESTAMP_CACHE_IN_BSS to include both ramstage and
postcar and uses this instead of ENV_RAMSTAGE to check for cache
location.
Ideally, it would be good to get rid of timestamp cache in postcar and
ramstage completely since early cbmem init is enabled by default in
coreboot and it is guaranteed that cbmem is recovered before
timestamps are added in ramstage or postcar. This change is being
pushed in as a temporary fix while I make the changes to remove
timestamp cache from romstage and postcar completely.
BUG=b:132939309
Change-Id: I2d82a96aba954df77c9386b7bd2e2ec0973881be
Signed-off-by: Furquan Shaikh <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32881
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Duncan Laurie <[email protected]>
Reviewed-by: Subrata Banik <[email protected]>
These Kconfigs are mostly used in src/lib/. Change-Id: I7aa5436c6ff5fef53fde2081e902d793f3581c1e Signed-off-by: Elyes HAOUAS <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32882 Reviewed-by: Nico Huber <[email protected]> Reviewed-by: Furquan Shaikh <[email protected]> Reviewed-by: Paul Menzel <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Save whether or not vboot has selected developer mode as a flag in vboot_working_data. Other coreboot code may access this flag without needing to consult vboot_handoff (which is in the process of being deprecated). BUG=b:124141368, b:124192753 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ieb6ac4937c943aea78ddc762595a05387d2b8114 Signed-off-by: Joel Kitching <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32843 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Patrick Georgi <[email protected]> Reviewed-by: Julius Werner <[email protected]>
vboot_measure_cbfs_hook() is included when CONFIG_VBOOT_MEASURED_BOOT is enabled, but this function is defined as 0 in vboot_crtm.h using ENV_ Remove ENV_ for vboot_measure_cbfs_hook() function definition. This function is added to bootblock stage also. BUG=NA TEST=Build Google Banon and Google Cyan Change-Id: Ic62c18db09c119dfb85340a6b7f36bfd148aaa45 Signed-off-by: Frans Hendriks <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32532 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Patrick Rudolph <[email protected]> Reviewed-by: Furquan Shaikh <[email protected]> Reviewed-by: Julius Werner <[email protected]>
New emmc DLL values for Casta BUG=b:122307918 TEST=Boot to OS on 12 systems Change-Id: Ie51885fb9628fa093ecc38f4a3f3157f751ca9ab Signed-off-by: Jamie Chen <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32799 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Furquan Shaikh <[email protected]> Reviewed-by: Karthik Ramasubramanian <[email protected]>
cbmem_find is not available in every stage. Remove usage of cbmem_find() and use GEN_PMCON1 always. BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Change-Id: Id97d57864b3e241e8f046d9b1caebdce199a46b1 Signed-off-by: Frans Hendriks <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32724 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Nico Huber <[email protected]>
The system should boot fine to OS on pressing power button before the system enters G3. However, on hatch, we observe that the system waits for few seconds at "Starting kernel" and then resets, with SD card tray inserted and SD_CD# pad reset config set to DEEP. Hence configuring SD_CD# pad reset config to PLTRST. BUG=b:129933011 TEST=Built and verified on hatch. Change-Id: Ic4466b96332f095ff39b28d98607e95fc3d12d6a Signed-off-by: Krishna Prasad Bhat <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32782 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Subrata Banik <[email protected]> Reviewed-by: Paul Fagerburg <[email protected]> Reviewed-by: Tim Wawrzynczak <[email protected]> Reviewed-by: Furquan Shaikh <[email protected]>
Apply commit d7b88dc (mb/google/x86-boards: Get rid of power button device in coreboot) to AMD Brazos boards [1]: > As per the ACPI specification, there are two types of power button > devices: > 1. Fixed hardware power button > 2. Generic hardware power button > > Fixed hardware power button is added by the OSPM if POWER_BUTTON flag > is not set in FADT by the BIOS. This device has its programming model > in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this > power button device by default if the power button FADT flag is not > set. > > On the other hand, generic hardware power button can be used by > platforms if fixed register space cannot be used for the power button > device. In order to support this, power button device object with HID > PNP0C0C is expected to be added to ACPI tables. Additionally, > POWER_BUTTON flag should be set to indicate the presence of control > method for power button. [..] > This change gets rid of the generic hardware power button from all > google mainboards and relies completely on the fixed hardware power > button. The same problem exists with the AMD Hudson devices in coreboot. For AMD Hudson (2) and Yangtze based devices this was removed in commit 44f2fab (AMD hudson and yangtze boards: Let mainboard declare power button) [2]. Two devices are detected. $ dmesg | grep Button [ 0.209213] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0 [ 0.209254] ACPI: Power Button [PWRB] [ 0.209332] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1 [ 0.209349] ACPI: Power Button [PWRF] $ sudo evtest No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Power Button /dev/input/event1: Power Button [..] [1]: https://review.coreboot.org/5546 [2]: https://review.coreboot.org/27272 Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497 Signed-off-by: Paul Menzel <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/27496 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Patrick Georgi <[email protected]> Reviewed-by: Stefan Reinauer <[email protected]>
It appears that the rebase.sh script was renamed to cross-repo-cherrypick and changed directories. Update comments to reflect that change. Change-Id: I863df48378feb48c9b195b1778dcaf1972a4f105 Signed-off-by: Jett Rink <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32849 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Patrick Georgi <[email protected]>
Add a new helper function die_with_post_code() that generates a post code and an error string prior to halting the CPU. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I87551d60b253dc13ff76f7898c1f112f573a00a2 Signed-off-by: Keith Short <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32838 Reviewed-by: Martin Roth <[email protected]> Reviewed-by: Aaron Durbin <[email protected]> Reviewed-by: Furquan Shaikh <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Change-Id: Idc165f8eafacf3130a29b701bc3610c1a67f69d5 Signed-off-by: Elyes HAOUAS <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32855 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Jacob Garber <[email protected]>
Add device identification D2:F1 for desktop version. (see Intel 945G/945GZ/945GC/945P/945PL Express Chipset Family datasheet page 192) Change-Id: Ie060644d635a7031ee6f55420d63751192481091 Signed-off-by: Elyes HAOUAS <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32877 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Lijian Zhao <[email protected]>
Adds support for the KB_ERR_CODE command on the Wilco EC. This command is used to drive diagnostic LEDs on the platform after a failed boot. This change also adds the Wilco EC mailbox command support to bootblock and verstage so that those stages can use the KB_ERR_CODE command. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I96d17baf57694e4e01c676d80c606f67054cd0c3 Signed-off-by: Keith Short <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32776 Reviewed-by: Duncan Laurie <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
This patch adds new function to perform gpio power management programming as per EDS. BUG=b:130764684 TEST=Able to build and boot from fixed media on ICL and CML. Change-Id: I816a70ad92595f013740a235a9799912ad51665e Signed-off-by: Subrata Banik <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32788 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Paul Fagerburg <[email protected]> Reviewed-by: Tim Wawrzynczak <[email protected]> Reviewed-by: Furquan Shaikh <[email protected]>
Provide option in chip.h to set dynamic local clock gating setting. BUG=b:130764684 TEST=Able to build and boot ICL. Change-Id: Ic30a490aadb8cc9c05a19a05533ab0196c69b7f1 Signed-off-by: Subrata Banik <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32789 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Furquan Shaikh <[email protected]>
Provide option in chip.h to set dynamic local clock gating setting. BUG=b:130764684 TEST=Able to build and boot CML. Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4 Signed-off-by: Subrata Banik <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32790 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Furquan Shaikh <[email protected]>
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration. GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D16 IRQ mapped for H1 TPM. BUG=b:130764684 TEST=H1 TPM interrupt working find and able to boot from fixed boot media Change-Id: I1f83f938f201c6574367960b1027555767cf6f3d Signed-off-by: Subrata Banik <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32847 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Furquan Shaikh <[email protected]>
…guration sarien/arcada: GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D18 IRQ mapped for H1 TPM. hatch: GPIO_COMM_0/1/2/3: Enable gpio community all PM configuration GPIO_COMM_4: Disable RCOMP clock gating due to GPP_C21 IRQ mapped for H1 TPM. BUG=b:130764684 TEST=H1 TPM interrupt working find and able to boot from fixed boot media Change-Id: Ia4d5483847a4d243b9038119d4bb5990591cc754 Signed-off-by: Subrata Banik <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32848 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Furquan Shaikh <[email protected]>
… 2018-02-09
This microcode update for CPU ID 0x700F01 improves system stability:
in particular, fixes Xen hardware virtualization freezes. Also it attempts to
patch some Spectre-related security vulnerabilities. This new microcode has been
tested by multiple coreboot community members and found working perfectly.
Old version: 0x700010B [2013-07-09]
replaced by
New version: 0x7000110 [2018-02-09]
Change-Id: Iebe6e54d922378a8a1feb97f37b08ac50c8234b2
Signed-off-by: Mike Banon <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28370
Reviewed-by: Martin Roth <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>
… 2018-03-05
This microcode update for CPU IDs 0x610F01/0x610F31 improves system stability:
in particular, fixes Xen hardware virtualization freezes. Also it attempts to
patch some Spectre-related security vulnerabilities. This new microcode has been
tested by multiple coreboot community members and found working perfectly.
Old version: 0x600110F [2012-01-11]
replaced by
New version: 0x600111F [2018-03-05]
Change-Id: Ied5da0ff85abb63c2db2eeafd051b8e00916d961
Signed-off-by: Mike Banon <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28273
Reviewed-by: Martin Roth <[email protected]>
Reviewed-by: <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>
When FSP UPD parameters are configured, also configure the GSPI CS lines appropriately. GSPI driver assumes CS0 is the CS signal to use. BUG=b:130329260 BRANCH=None TEST=Boot Kohaku, TPM communcation still functional. Change-Id: Ic816395b7d198a52c704e6cabcb56889150b741c Signed-off-by: Tim Wawrzynczak <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32791 Reviewed-by: Patrick Georgi <[email protected]> Reviewed-by: Paul Fagerburg <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Probably a copy/paste issue. Change-Id: I0334bc1f5d145df5af0a307cf8e7c23cc0605f76 Signed-off-by: Elyes HAOUAS <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32886 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Furquan Shaikh <[email protected]>
All variants (t400, r400, t500, w500) use the same OPROM for the IGD. Change-Id: I1b9db7b29b22809542f80f60a5e2eb3283fe1c02 Signed-off-by: Arthur Heymans <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32884 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Paul Menzel <[email protected]> Reviewed-by: Patrick Rudolph <[email protected]>
Tested: - Ethernet NIC - Wifi RFKill - USB - LVDS, VGA with libgfxinit - Booting with dock attached (COM1) - Keyboard, trackpoint - SeaBIOS 1.12 - S3 resume - Tested in descriptor mode, with vendor FD and ME - Add VBT to ACPI OPregion Untested: - SATA (likely works) - Trackpad (my cable is broken, likely works) - Displayport (likely works) - Descriptorless mode - DVD drive - Extra battery - model with ATI GPU Does not work: - Dock hotplug - Quad core CPU (hangs during AP init, probably needs hardware mod) - Hotplugging the expresscard slot (works with 'echo 1 | sudo tee /sys/bus/pci/rescan') TODO: - proper dock support - documentation note: This board was hard to flash, I had to desolder the flash. TESTED: on a R500 with an Intel iGPU, SeaBIOS 1.12, Debian 9, Linux 4.9 from USB Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815 Signed-off-by: Arthur Heymans <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28644 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Patrick Rudolph <[email protected]>
Currently DT paths are *not* expected to start with '/'. This is not what the spec says (see Devicetree Specification v0.2, 2.2.3 Path Names) and also not what is done by Linux. Change dt_find_node_by_path() to expect paths to start with '/' and add a leading '/' to all DT path strings. Besides the compatibility with the spec this change is also needed to support aliases in the future. This patch was adapted from depthcharge's http://crosreview.com/1252770 Change-Id: Ibdf59ccbb4ead38c6193b630642fd1f1e847dd89 Signed-off-by: Julius Werner <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32865 Reviewed-by: Hung-Te Lin <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
This patch adds support to lookup nodes via the "/aliases" mechanism in device trees. This may be required for overlay support (don't quite remember tbh) and is also just a generally useful feature. It was adapted from depthcharge's http://crosreview.com/1249703 and http://crosreview.com/1542702. Change-Id: I1289ab2f02c4877a2d0111040384827e2b48a34a Signed-off-by: Julius Werner <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32866 Reviewed-by: Hung-Te Lin <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
This patch updates the device tree dumping functions (not compiled by default but available for debugging) to output properties and nodes in a format similar to .dts files that is very close to what dtc outputs when you decompile a .dtb with it. This makes it easier to match device tree dumps from coreboot with device tree dumps generated by other device tree tooling. This patch was adapted from depthcharge's http://crosreview.com/1536386 Change-Id: Ib40e50d906aff05473a70c4fc9b124d63232558c Signed-off-by: Julius Werner <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32867 Reviewed-by: Hung-Te Lin <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
FDT property data should not be const -- sometimes we need to update it, for example when fixing up phandles in an overlay. On the other hand it's occasionally desirable to put a string constant in there without having to strdup() it all the time... let's just live with the tiny implicit assumption that the data we'd want to modify (phandle references, mostly) will never be added from string constants, and put a cast in dt_add_string_prop(). Change-Id: Ifac103fcff0520cc427ab9a2aa141c65e12507ac Signed-off-by: Julius Werner <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32868 Reviewed-by: Hung-Te Lin <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
The code in cpu/intel/car/romstage.c Does most of the things like setting up timestamps, stack guards, entering postcar. A functional difference is that the FSP header is searched for twice instead of passed from the CAR entry to the C code. When using C_ENVIRONMENT_BOOTBLOCK this needs to be done anyway (or a special linker symbol kept across multiple stages is needed, which is likely not worth the speedup). Change-Id: I0f03e5a808f00157fdd807b104417a54e4bde7b2 Signed-off-by: Arthur Heymans <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32963 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Kyösti Mälkki <[email protected]>
Change-Id: Iab8d20a385bde31b29fa7766a87753fcc2d759b8 Signed-off-by: Felix Singer <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32544 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Felix Held <[email protected]>
It's GPIO28 according to schematics. Change-Id: I55be1ed178c818a17766e22cb2fd010412b8fe02 Signed-off-by: Evgeny Zinoviev <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33149 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Nico Huber <[email protected]> Reviewed-by: Felix Held <[email protected]>
As long as we keep the IS_ENABLED() definition in libpayload for compatibility, we should check that IS_ENABLED() usage doesn't sneak back in. Also remove all other IS_ENABLED() checks. Change-Id: Id30ffa0089cec6c24fc3dbbb10a1be35f63b3d89 Signed-off-by: Nico Huber <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32229 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Julius Werner <[email protected]> Reviewed-by: Patrick Georgi <[email protected]>
Change-Id: I13d6593e283f0a9e6603e19ccfda116f3b145e52 Signed-off-by: Elyes HAOUAS <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32948 Reviewed-by: Felix Held <[email protected]> Reviewed-by: Kyösti Mälkki <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
We keep its definition in libpayload, though, to maintain compatibility with existing payload code. For now. Change-Id: I8fc0d0136ba2316ef393c5c17f2b3ac3a9c6328d Signed-off-by: Nico Huber <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32230 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Julius Werner <[email protected]>
TEST=build Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Signed-off-by: Prudhvi Yarlagadda <[email protected]> Signed-off-by: Sricharan R <[email protected]> Signed-off-by: Nitheesh Sekar <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29957 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Patrick Georgi <[email protected]>
Add support for UART driver in coreboot. TEST=build & run Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Signed-off-by: Prudhvi Yarlagadda<[email protected]> Signed-off-by: Sricharan R <[email protected]> Signed-off-by: Nitheesh Sekar <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29964 Reviewed-by: Stefan Reinauer <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Add SPI driver support in coreboot. Change-Id: I813ba0b5cc8344c463c3e41ff6db80bc0d8ebd96 Signed-off-by: Prudhvi Yarlagadda <[email protected]> Signed-off-by: Nitheesh Sekar <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32058 Reviewed-by: Patrick Georgi <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
BUG=b:133389422
TEST=check SSD's power off sequence to meet PCIE requirement.
SSD's reset should be cleared before clearing SSD's power EN Pin.
Change-Id: Ia106b805deafb8a442b56bcce91b51135cb32988
Signed-off-by: Roy Mingi Park <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33182
Reviewed-by: EricR Lai <[email protected]>
Reviewed-by: Duncan Laurie <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>
Some variants only support 4 PCIe ports so there is no need to have those unavailable ports in the devicetree. Change-Id: I154cae358fb7f862fc0c8eaa620474b37b5e6484 Signed-off-by: Arthur Heymans <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30821 Reviewed-by: Felix Held <[email protected]> Reviewed-by: Angel Pons <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Change-Id: I3d743e90444292be687999ab4f50aa89d514fbad Signed-off-by: Arthur Heymans <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33171 Reviewed-by: Felix Held <[email protected]> Reviewed-by: Angel Pons <[email protected]> Reviewed-by: HAOUAS Elyes <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Clang Static Analyzer version 8.0.0 detects null pointer argument in call to memory copy function. Add sanity check for pointer header to prevent null pointer dereference. TEST=Built and boot up to kernel. Change-Id: I7027b7cae3009a5481048bfa0536a6cbd9bef683 Signed-off-by: John Zhao <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33051 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Lance Zhao <[email protected]> Reviewed-by: Felix Held <[email protected]>
Change-Id: I142ae6f7806b3f57b98a158e8f26592aed8fa452 Signed-off-by: Elyes HAOUAS <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32939 Reviewed-by: Felix Held <[email protected]> Reviewed-by: Kyösti Mälkki <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Coverity detects pointer fih as FORWARD_NULL. Add sanity check for fih to prevent NULL pointer dereference. BUG=CID 1401717 TEST=Built and boot up to kernel. Change-Id: Ia6853e5302c87d9ffe52b942f067be56f6e77406 Signed-off-by: John Zhao <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33150 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Felix Held <[email protected]> Reviewed-by: Christian Walter <[email protected]>
hexdump() is not available in postcar stage. Add hexdump() functionality to postcar stage. BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Change-Id: Ibdce911065c01b0a1aa81dc248557257d0e420b0 Signed-off-by: Frans Hendriks <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32908 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: David Hendricks <[email protected]>
Initial support for Facebook FBG-1701 system. coreboot implementation based on Intel Strago mainboard. Configure 'Onboard memory manufacturer' which must match HW. BUG=N/A TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701 Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Signed-off-by: Frans Hendriks <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: David Hendricks <[email protected]> Reviewed-by: Patrick Rudolph <[email protected]>
Add maintainers to the new mainboard port. Change-Id: I620ea424cc26fa0218a74052863ea30700789e1b Signed-off-by: Frans Hendriks <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33224 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Philipp Deppenwiese <[email protected]>
Signed-off-by: Krystian Hebel <[email protected]>
32-bit code can still be run with i386_do_exec() - it is run in true protected mode, not compatibility mode. Exceptions were tested with #DE, #GP and #DB. Apparently BSS is not cleared by SeaBIOS, it needs to be cleared manually. This operation can take some time, depending mostly on stack/heap size. Signed-off-by: Krystian Hebel <[email protected]>
Signed-off-by: Krystian Hebel <[email protected]>
All include/* files were obtained from Bareflank commit ba613e2c687f Signed-off-by: Krystian Hebel <[email protected]>
Signed-off-by: Krystian Hebel <[email protected]>
Signed-off-by: Krystian Hebel <[email protected]>
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