🎓 Electronics & Communication Engg | 8th Sem | KS School of Engineering
💼 PD Intern @ ACL Digital | VLSI
👥 Ex-Treasurer, IEEE Sensors Council | Rotaract RACKSSEM
- 🔧 VLSI Design (Verilog, Cadence Genus/Innovus, Timing Analysis)
- 📊 Signal Processing (MATLAB, Python, FFT Implementation)
- 🏗️ Physical Design (Placement, CTS, Power Planning)
| Project | Tech Stack | Key Achievement | Links |
|---|---|---|---|
| AXI-Stream DSP Accelerator | Verilog, SPST Multiplier, Cadence Genus | >7ps positive slack, Low-power FFT pipeline |  |
| Li-Fi Text Transmission | LED/Photodiode, Embedded C | Secure visible light communication |  |
| Order Filter (DIP) | MATLAB, Digital Image Processing | Spatial filtering for image denoising & enhancement |  |
"Building efficient hardware, one gate at a time." 💻⚡