This work was conducted by students at UCSD, POSTECH, and Drexel to help enable fundamental research in EDA using the NanGate45 open-source PDK and the NanGate Open Cell Library. When the NanGate45 research enablement was first released (e.g., https://eda.ncsu.edu/downloads), only Cadence enablement was provided. As a result, researchers have not been able to perform post-route extraction and timing, or timing-driven P&R, using Synopsys tools. Our work develops and makes public .tluplus and other necessary design enablement so that post-route extraction and timing, as well as timing-driven P&R, are possible for Synopsys tool users. We provide testcases and example scripts showing “reasonable” correlation of our new Synopsys enablement to the previously-existing Cadence enablement. Importantly, please note that indicators of correlation that we present are not, and should not be construed as, "benchmarking" of any kind. We make no value judgments regarding the respective merits of commercial EDA tools. We welcome suggestions for improvement or improved materials to be included in this repository; please communicate these by email or use GitHub issues, pull requests, etc. Our contact information is provided below. Last, please note and read carefully the headers of all TCL files in this repository that invoke commercial EDA tools. We thank both Cadence and Synopsys for allowing their copyrighted IP to be made publicly available for use by researchers in this manner.
- Andrew B. Kahng ([email protected])
- Seokhyeong Kang ([email protected])
- Jakang Lee ([email protected])
- Ioannis Savidis ([email protected])
- Pratik Shrestha ([email protected])
- Dooseok Yoon ([email protected])
- Design Enablement
- Validation of Design Enablement
- Experimental Results
- Usage and Running Instructions
- References
- Appendix
The files required for design implementation are as follows.
| Cadence | Synopsys | |
|---|---|---|
| Physical library | LEF | LEF |
| Technology library | LEF | TF |
| Liberty library | LIB | DB |
| Interconnect File | ICT | ITF |
| RC Lookup Table | CAPTABLE | TLU+ |
| Parasitic Extraction | QRC | NXTGRD |
All enablements, except for Synopsys enablement, are taken from [1]. Additionally, this repository includes .tf files (modified from [2]), as well as .db, .itf, .ict, .tluplus, and .nxtgrd files.
To validate the Synopsys enablement that we provide, we conduct experiments comparing the results from the flows of two EDA companies (i.e., Synopsys and Cadence) under various conditions. The evaluation metrics we use are as follows:
- Number of Matching Timing Paths. This metric is based on the endpoint timing information output by both tools. It measures the consistency of PEX and STA engines between the two tools.
- Net Capacitance. The capacitance of all nets in the design. This metric can be further categorized based on whether coupling capacitance is present.
- Timing Details for Each Endpoint. The characteristics of all timing endpoints in the design, based on setup analysis. These values can be further categorized based on whether the options for coupling capacitance extraction and signal integrity analysis are enabled.
- Actual Arrival Time
- Worst Slack
- Each Cell Delay
- Each Wire Delay
- Each Cell Output Slew
- Each Wire Output Slew
Timing details vary depending on the design stage and the tools we use.
- Flow 1: Embedded PEX in P&R tool, and embedded STA in P&R tool
- Flow 2: Embedded PEX in P&R tool, and Standalone STA
- Flow 3: Standalone PEX, and Standalone STA
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Flow 1: This flow uses the embedded PEX and STA engines in each P&R tool as-is, juxtaposing the results from Cadence Innovus and Synopsys Fusion Compiler.
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Flow 2: In this flow, the embedded PEX engine of each P&R tool is used as-is, while the STA analysis is performed with the same tool (Synopsys PrimeTime). By fixing the STA engine, only the differences between the PEX engines are analyzed. In this flow, we use the SPEF files generated by Cadence Innovus and Synopsys Fusion Compiler as input for Synopsys PrimeTime. (Note that we have also implemented a symmetric flow that uses Cadence Tempus. The fact that we discuss Synopsys PrimeTime here in no way implies any preference or value judgment. For the Cadence Tempus-based flow, please refer to the instructions below.)
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Flow 3: This flow independently utilizes both the PEX and STA engines for analysis, employing Cadence Quantus and Tempus alongside Synopsys StarRC and PrimeTime.
We must note that when extracting timing paths from different tools, the timing paths reported for given endpoints and/or for given analysis requests do not always exactly match. Therefore, for the purpose of comparing the characteristics of the timing paths in our experiment, we define ‘matching timing path types’ as follows:
- Case 1: The timing paths from both tools have the same cells and transition types (i.e., rise, fall).
- Case 2: The timing paths from both tools consist of the same cells but have different transition types.
- Case 3: At least one cell in the timing paths differs between the two tools.
In this repository, we use only Cases 1 and 2 for comparison and evaluation.
The figure below shows the path matching types in our repository:
We summarize the experimental results using tables and plots. The plots presented here have been selected as representative examples for validation scenarios of interest. Data and plots can be directly examined, either by following usage instructions below to extract the data yourself, or by checking the files that have been uploaded in the "benchmark" directory.
We use “absolute difference” for evaluation because the scale of the data we handle is very small, and use of relative difference would lead to data distortion. However, since absolute difference is expressed in absolute terms, its value varies depending on the range of the data. Therefore, when reporting our results here, we use “Normalized Absolute difference.” This is simply the mean or the maximum absolute difference, divided by the data range. Here, data range is defined as the difference between the maximum and minimum values across all data points from both groups being compared.
The formula is as follows:
Normalized Absolute Difference = Absolute Difference / (Maximum - Minimum)
The abbreviations used in the experimental report have the following meanings:
- DESIGN: The name of the top module in the benchmark.
- CC: Whether or not to include and extract the “Coupling Capacitance” (CC) during parasitic extraction.
- SI: Whether or not to enable “Signal Integrity” (SI) analysis during static timing analysis.
- INVS: Innovus
- FC: Fusion Compiler
- QTS: Quantus
- TPS: Tempus
- STRC: StarRC
- PT: PrimeTime
- PEX: Parasitic Extraction Engine
- STA: Static Timing Analysis Engine
-
Number of Matching Timing Paths
Statistics for paths that match both Case 1 and Case 2.-
Flow 1:
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When coupling capacitance extraction and signal integrity analysis are disabled:
- Lowest matching rate: 64 % (IBEX)
- Average matching rate: 88.41 %
- Highest matching rate: 98.68 % (LDPC)
-
When coupling capacitance extraction and signal integrity analysis are enabled:
- Lowest matching rate: 59.07 % (IBEX)
- Average matching rate: 77.69 %
- Highest matching rate: 97.08 % (JPEG)
-
-
Flow 2:
-
When coupling capacitance extraction and signal integrity analysis are disabled:
- Lowest matching rate: 78.21 % (IBEX)
- Average matching rate: 92.70 %
- Highest matching rate: 98.83 % (LDPC)
-
When coupling capacitance extraction and signal integrity analysis are enabled:
- Lowest matching rate: 68.85 % (LDPC)
- Average matching rate: 81.11 %
- Highest matching rate: 98.56 % (JPEG)
-
-
Flow 3:
- When coupling capacitance extraction and signal integrity analysis are enabled:
- Lowest matching rate: 58.31 % (IBEX)
- Average matching rate: 79.72 %
- Highest matching rate: 96.79 % (JPEG)
- When coupling capacitance extraction and signal integrity analysis are enabled:
-
Summary: Consolidating the results from the three flows, we observe that the average matching rates range from approximately 77.7% to 92.7%. Overall, our implemented Synopsys enablement achieves an average timing path matching rate of about 83.93% compared to Cadence enablement.
-
-
Net Capacitance
The average net capacitance comparison results across all designs are as follows:- R2 score: 0.9957
- mean normalized absolute difference: 0.09 %
- maximum normalized absolute difference: 7.71 %
-
Timing Details for Each Endpoint
The table in the Appendix Section summarizes the comparison results for Actual Arrival Time (AAT) and Slack in Timing Path Matching Case 1. Overall, across all designs:-
AAT:
- R2 score: 0.9993
- Mean normalized absolute difference: 0.37 %
- Maximum normalized absolute difference: 3.92 %
-
Slack:
- R2 score: 0.9991
- Mean normalized absolute difference: 0.37 %
- Maximum normalized absolute difference: 6.82 %
-
If you want to run the predefined studies, please use:
Usage) ./run.sh
If you want to run with a custom combination:
Example) make DESIGN=ldpc_decoder_mod PEX_TOOL1=innovus STA_TOOL1=innovus CC1=true SI1=true PEX_TOOL2=fusion_compiler STA_TOOL2=fusion_compiler CC2=true SI2=true CASE=1
The execution results are stored in the "benchmark/(your_design_name)" directory.
Our repository is composed of the following files and directories:
- NanGate45: Directory containing design enablement for Cadence and Synopsys.
- benchmark: The design directory that we used for evaluation:
- Input files for Extracting Design Data
- DEF file with routing
- Flattened netlist file after routing stage
- SDC file with all input/output port constraints
- Output files
- SPEF files
- CSV files of net capacitance
- CSV files of timing details
- summary files
- plot
- done: A directory that collects files used to verify the completion of a particular step in the Makefile. In particular, it deals with generating data tables and plots.
- Input files for Extracting Design Data
- scripts: This directory contains EDA tool scripts that allow users to run PEX and STA according to their preferences.
- Makefile: Users can process data from various tools they wish to compare using the make command. This Makefile performs the following functions:
- It executes the user-selected PEX tool and STA tool to generate CSV files containing net capacitance and timing details. Since two types of data are required for comparison, users must define two flow types (please refer to the example parameters below).
- It reads the generated CSV files and produces evaluation metrics such as plots, R2 scores, and absolute differences.
- Parameters
- DESIGN: The top-level block name defined in the DEF and netlist.
- PEX_TOOL1 / PEX_TOOL2: The PEX Engine for extracting the SPEF file. The allowed values are "innovus", "quantus", "fusion_compiler", and "starRC". Innovus utilizes TQuantus which is the built-in PEX engine.
- STA_TOOL1 / STA_TOOL2: The STA engine for extracting timing details. The allowed values are "innovus", "tempus", "fusion_compiler", and "PrimeTime".
- CC1 / CC2: Whether to extract coupling capacitance along with the SPEF when using the PEX Engine. The allowed values are "true", "false".
- SI1 / SI2: Whether to extract timing details with signal integrity analysis in the STA engine. The allowed values are "true", "false".
- NWORST: The maximum number of worst paths to extract at each endpoint. This is typically set to 1. The allowed values are the number over one.
- CASE: Which matched path type to assume when extracting timing details (please refer to the aforementioned "path matching type"). The allowed values are "1", "2".
- run.sh: The file that defines the presets used in the experiment.
To extract as many timing paths as possible, we add the following constraints to the SDC. These constraints intentionally apply timing constraints to the primary input/output ports so that they are considered as timing paths during STA.
- set_input_delay -clock [get_clocks $clock_name] 0.0 [all_inputs]
- set_output_delay -clock [get_clocks $clock_name] 0.0 [all_outputs]
Additionally, since Fusion Compiler allows timing borrowing in latch timing analysis by default while Innovus does not, we recommend adding the following constraint to facilitate comparison under identical analysis conditions. (Optional)
- set_max_time_borrow 0 [all_registers]
The figure below shows the types of timing paths that we extract.
For commercial EDA tools, we used the versions below.
[Cadence]
- Innovus: 21.1
- Quantus: 21.1
- Tempus: 21.1
[Synopsys]
- Fusion Compiler: 22.3
- PrimeTime: 18.6
- StarRC: 18.6
[1] NanGate45 from TILOS-AI-Institute/MacroPlacement's github
[2] Synopsys tech file (.tf) from mflowgen/freepdk-45nm
- Flow 1
| DESIGN | CC & SI | # of timing paths | # of matched timing paths [Case 1 + Case 2] |
|---|---|---|---|
| AES | OFF | 1444 | 1368 (94.74 %) |
| ON | 1241 (85.94 %) | ||
| IBEX | OFF | 4925 | 3152 (64.00 %) |
| ON | 2909 (59.07 %) | ||
| JPEG | OFF | 12131 | 11771 (97.03 %) |
| ON | 11777 (97.08 %) | ||
| LDPC | OFF | 6145 | 6064 (98.68 %) |
| ON | 4123 (67.10 %) | ||
| Ariane133 | OFF | 62086 | 50845 (81.89 %) |
| ON | 50039 (80.60 %) | ||
| NVDLA part c |
OFF | 122999 | 115792 (94.14 %) |
| ON | 93906 (76.35 %) |
- Flow 2
| DESIGN | CC & SI | # of timing paths | # of matched timing paths [Case 1 + Case 2] |
|---|---|---|---|
| AES | OFF | 1444 | 1394 (96.54 %) |
| ON | 1232 (85.32 %) | ||
| IBEX | OFF | 4925 | 3852 (78.21 %) |
| ON | 3406 (69.16 %) | ||
| JPEG | OFF | 12131 | 11942 (98.44 %) |
| ON | 11956 (98.56 %) | ||
| LDPC | OFF | 6145 | 6073 (98.83 %) |
| ON | 4231 (68.85 %) | ||
| Ariane133 | OFF | 62086 | 54195 (87.29 %) |
| ON | 54237 (87.36 %) | ||
| NVDLA part c |
OFF | 122999 | 119180 (96.90 %) |
| ON | 95179 (77.38 %) |
- Flow 3
| DESIGN | CC & SI | # of timing paths | # of matched timing paths [Case 1 + Case 2] |
|---|---|---|---|
| AES | ON | 1444 | 1209 (83.73 %) |
| IBEX | ON | 4925 | 2872 (58.31 %) |
| JPEG | ON | 12131 | 11741 (96.79 %) |
| LDPC | ON | 6145 | 4144 (67.44 %) |
| Ariane133 | ON | 62086 | 46865 (75.48 %) |
| NVDLA part c |
ON | 122999 | 118787 (96.58 %) |
| DESIGN | Cadence's PEX ↔ Synopsys's PEX | CC | R2 | Normalized Absolute Difference | ||
|---|---|---|---|---|---|---|
| Mean | Std | Max | ||||
| AES | INVS ↔ FC | OFF | 0.9966 | 0.13% | 0.22% | 5.53% |
| ON | 0.9968 | 0.13% | 0.22% | 5.54% | ||
| QTS ↔ STRC | ON | 0.9965 | 0.15% | 0.22% | 5.81% | |
| IBEX | INVS ↔ FC | OFF | 0.9955 | 0.13% | 0.42% | 13.81% |
| ON | 0.9955 | 0.12% | 0.42% | 14.36% | ||
| QTS ↔ STRC | ON | 0.9952 | 0.22% | 0.46% | 6.46% | |
| JPEG | INVS ↔ FC | OFF | 0.9929 | 0.05% | 0.23% | 10.11% |
| ON | 0.9925 | 0.05% | 0.24% | 10.45% | ||
| QTS ↔ STRC | ON | 0.9956 | 0.07% | 0.16% | 5.52% | |
| LDPC | INVS ↔ FC | OFF | 0.9961 | 0.11% | 0.25% | 5.69% |
| ON | 0.9963 | 0.10% | 0.24% | 5.53% | ||
| QTS ↔ STRC | ON | 0.9962 | 0.12% | 0.26% | 5.26% | |
| Ariane133 | INVS ↔ FC | OFF | 0.9947 | 0.07% | 0.34% | 13.00% |
| ON | 0.9945 | 0.07% | 0.34% | 13.28% | ||
| QTS ↔ STRC | ON | 0.9961 | 0.12% | 0.31% | 5.78% | |
| NVDLA part c | INVS ↔ FC | OFF | 0.9988 | 0.00% | 0.01% | 0.84% |
| ON | 0.9980 | 0.00% | 0.01% | 3.47% | ||
| QTS ↔ STRC | ON | 0.9948 | 0.00% | 0.02% | 8.30% | |
The plot below shows the "worst-case" (i.e., in the sense of exhibiting largest deviations between analysis scenarios) comparisons for mean normalized absolute difference and for maximum normalized absolute difference.
| DESIGN | FLOW | CC & SI | Actual Arrival Time | Slack | ||||
|---|---|---|---|---|---|---|---|---|
| R2 | Normalized Absolute Difference | R2 | Normalized Absolute Difference | |||||
| Mean | Max | Mean | Max | |||||
| AES | 1 | OFF | 0.9999 | 0.25% | 1.22% | 0.9999 | 0.25% | 1.17% |
| ON | 0.9991 | 0.51% | 5.31% | 0.9991 | 0.53% | 5.47% | ||
| 2 | OFF | 0.9999 | 0.24% | 1.04% | 0.9999 | 0.25% | 1.13% | |
| ON | 0.9993 | 0.38% | 6.13% | 0.9993 | 0.40% | 6.19% | ||
| 3 | ON | 0.9984 | 0.66% | 7.05% | 0.9984 | 0.68% | 7.16% | |
| IBEX | 1 | OFF | 0.9999 | 0.15% | 0.81% | 0.9976 | 0.20% | 44.04% |
| ON | 0.9996 | 0.24% | 3.26% | 0.9962 | 0.29% | 46.82% | ||
| 2 | OFF | 0.9999 | 0.19% | 0.73% | 0.9999 | 0.20% | 0.76% | |
| ON | 0.9996 | 0.35% | 3.40% | 0.9995 | 0.36% | 3.50% | ||
| 3 | ON | 0.9997 | 0.23% | 2.44% | 0.9997 | 0.23% | 2.54% | |
| JPEG | 1 | OFF | 0.9999 | 0.23% | 1.34% | 0.9999 | 0.23% | 1.35% |
| ON | 0.9999 | 0.24% | 2.65% | 0.9999 | 0.23% | 2.81% | ||
| 2 | OFF | 0.9999 | 0.18% | 0.94% | 0.9999 | 0.19% | 0.98% | |
| ON | 0.9999 | 0.16% | 2.26% | 0.9999 | 0.16% | 2.34% | ||
| 3 | ON | 0.9992 | 0.65% | 2.61% | 0.9992 | 0.63% | 2.67% | |
| LDPC | 1 | OFF | 0.9991 | 0.79% | 2.57% | 0.9991 | 0.80% | 2.59% |
| ON | 0.9984 | 0.40% | 9.61% | 0.9985 | 0.40% | 9.34% | ||
| 2 | OFF | 0.9990 | 0.82% | 2.40% | 0.9991 | 0.80% | 2.35% | |
| ON | 0.9989 | 0.47% | 6.89% | 0.9990 | 0.47% | 6.68% | ||
| 3 | ON | 0.9981 | 0.59% | 6.82% | 0.9984 | 0.57% | 6.65% | |
| Ariane133 | 1 | OFF | 0.9999 | 0.06% | 0.44% | 0.9999 | 0.07% | 0.45% |
| ON | 0.9995 | 0.11% | 2.52% | 0.9995 | 0.11% | 2.55% | ||
| 2 | OFF | 0.9999 | 0.06% | 0.39% | 0.9999 | 0.06% | 0.39% | |
| ON | 0.9998 | 0.07% | 1.11% | 0.9998 | 0.07% | 1.12% | ||
| 3 | ON | 0.9989 | 0.21% | 1.62% | 0.9989 | 0.21% | 1.63% | |
| NVDLA part c |
1 | OFF | 0.9997 | 0.33% | 4.20% | 0.9997 | 0.34% | 4.33% |
| ON | 0.9960 | 0.88% | 14.90% | 0.9960 | 0.86% | 14.97% | ||
| 2 | OFF | 0.9998 | 0.26% | 4.11% | 0.9998 | 0.26% | 4.31% | |
| ON | 0.9997 | 0.23% | 6.05% | 0.9997 | 0.23% | 6.03% | ||
| 3 | ON | 0.9972 | 1.08% | 12.63% | 0.9973 | 1.05% | 12.41% | |
For IBEX in Flow 1, the Slack comparison shows outliers—with the maximum normalized absolute difference reaching a very high value (44–47%). With Flow 2, this phenomenon is not observed. Such a difference may be due to differences between STA engine algorithms or implementations. This said, our focus in this work is solely to provide wire parasitic component modeling files for use of Synopsys tools with NanGate45.
The plot below shows the Slack results for IBEX in Flow 1 and Flow 2, with outliers highlighted by red dotted lines.
The following plot shows the "worst-case" comparisons for mean normalized absolute difference and for maximum normalized absolute difference, excluding outlier cases.
