ACMClassCourses · jpppppppppppppppppppppppp · Jan 1, 2024
diff --git a/W11D1.md b/W11D1.md
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+![image-20240101164856396](./pic/image-20240101164856396.png)
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+为什么要有Memory Reorder Buffer:为了保证多核之间的写一致性，如Write Barrier和Read Barrier。
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+芯片上电源和时钟部件的位置很关键。$P=CV^2 f$，整个机器的功耗与时钟频率成正相关。
diff --git a/W15D1.md b/W15D1.md
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+<img src="./pic/image-20240101173149770.png" alt="image-20240101173149770" style="zoom:200%;" />
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+1. Core + Cache (V) + VM
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+   synonym & alias problem: page table per process
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+2. Core + VM + Cache (P)
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+   performance problem: TLB (translation lookaside buffer)
diff --git a/W6D2.md b/W6D2.md
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+2:1规则：提高关联度，至于要一半的大小，可以实现相近的miss rate（小范围成立）
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+![image-20240101150700234](./pic/image-20240101150700234.png)
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+![image-20240101150748620](./pic/image-20240101150748620.png)
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+Miss Rate先减小（能够更好地利用 spatial locality ）后增大（more conflicts and capacity misses）
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+![image-20240101151144771](./pic/image-20240101151144771.png)
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+命中逻辑复杂，可能会增加时钟周期，导致最终的AMAT增加
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+![image-20240101151646084](./pic/image-20240101151646084.png)
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+对替换掉的Cache lines做一个回收的处理
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+![image-20240101155003823](./pic/image-20240101155003823.png)
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+![image-20240101154951193](./pic/image-20240101154951193.png)
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+![image-20240101155509933](./pic/image-20240101155509933.png)
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+![image-20240101160058894](./pic/image-20240101160058894.png)
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+![image-20240101160519951](./pic/image-20240101160519951.png)
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+<img src="./pic/image-20240101160543161.png" alt="image-20240101160543161" style="zoom: 67%;" />
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+![image-20240101160602705](./pic/image-20240101160602705.png)![image-20240101160609673](./pic/image-20240101160609673.png)
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