RISCV64: SG2042: HACK: ttm: disallow cached mapping

FIXME: this hack fixed the issue when booting PCIe radeon GPU card,
it will report:
[    2.909876] [drm:r600_ring_test] *ERROR* radeon: ring 0 test failed (scratch(0x8504)=0xCAFEDEAD)

Rootcasue Analysis:
The radeon/amdgpu driver expects pcie to snoop cpu cache, which
means the contents of cpu cache should also be seen by pcie.
But sg2042 does not meet this requirement. When the GPU is being
initialized, the GPU's ring_test tries to write a value to a
certain memory address, and then read back to check whether it
is written in (before that, the cpu writes another value in).
Due to SG2042's issue, gpu cannot snoop cpu cache, check fails.

The hack solution is to change the memory mapped by the ttm
memory manager to uncached mode to workaround this SoC issue.

Signed-off-by: Icenowy Zheng <[email protected]>
Tested-by: Chen Wang <[email protected]>
Signed-off-by: Han Gao <[email protected]>

Author: Icenowy

drivers/gpu/drm/drm_gem_vram_helper.c

@@ -797,8 +797,11 @@ static struct ttm_tt *bo_driver_ttm_tt_create(struct ttm_buffer_object *bo,
 	tt = kzalloc(sizeof(*tt), GFP_KERNEL);
 	if (!tt)
 		return NULL;
-
+#if !defined(CONFIG_PCIE_SG2042_HACK)
 	ret = ttm_tt_init(tt, bo, page_flags, ttm_cached, 0);
+#else
+	ret = ttm_tt_init(tt, bo, page_flags, ttm_write_combined, 0);
+#endif
 	if (ret < 0)
 		goto err_ttm_tt_init;
 

drivers/gpu/drm/ttm/ttm_bo_util.c

@@ -355,6 +355,7 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo,
 	if (ret)
 		return ret;
 
+#if !defined(CONFIG_PCIE_SG2042_HACK)
 	if (num_pages == 1 && ttm->caching == ttm_cached &&
 	    !(man->use_tt && (ttm->page_flags & TTM_TT_FLAG_DECRYPTED))) {
 		/*
@@ -366,6 +367,8 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo,
 		map->page = ttm->pages[start_page];
 		map->virtual = kmap(map->page);
 	} else {
+#endif
+	{
 		/*
 		 * We need to use vmap to get the desired page protection
 		 * or to make the buffer object look contiguous.

drivers/gpu/drm/ttm/ttm_resource.c

@@ -335,7 +335,11 @@ void ttm_resource_init(struct ttm_buffer_object *bo,
 	res->bus.addr = NULL;
 	res->bus.offset = 0;
 	res->bus.is_iomem = false;
+#if !defined(CONFIG_PCIE_SG2042_HACK)
 	res->bus.caching = ttm_cached;
+#else
+	res->bus.caching = ttm_write_combined;
+#endif
 	res->bo = bo;
 
 	man = ttm_manager_type(bo->bdev, place->mem_type);
@@ -839,16 +843,22 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io,
 	} else {
 		iter_io->needs_unmap = true;
 		memset(&iter_io->dmap, 0, sizeof(iter_io->dmap));
+#if !defined(CONFIG_PCIE_SG2042_HACK)
 		if (mem->bus.caching == ttm_write_combined)
+#else
+		if (mem->bus.caching == ttm_write_combined || mem->bus.caching == ttm_cached)
+#endif
 			iosys_map_set_vaddr_iomem(&iter_io->dmap,
 						  ioremap_wc(mem->bus.offset,
 							     mem->size));
+#if !defined(CONFIG_PCIE_SG2042_HACK)
 		else if (mem->bus.caching == ttm_cached)
 			iosys_map_set_vaddr(&iter_io->dmap,
 					    memremap(mem->bus.offset, mem->size,
 						     MEMREMAP_WB |
 						     MEMREMAP_WT |
 						     MEMREMAP_WC));
+#endif
 
 		/* If uncached requested or if mapping cached or wc failed */
 		if (iosys_map_is_null(&iter_io->dmap))

drivers/gpu/drm/ttm/ttm_tt.c

@@ -158,7 +158,11 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm,
 	ttm->dma_address = NULL;
 	ttm->swap_storage = NULL;
 	ttm->sg = bo->sg;
+#if !defined(CONFIG_PCIE_SG2042_HACK)
 	ttm->caching = caching;
+#else
+	ttm->caching = ttm_write_combined;
+#endif
 	ttm->restore = NULL;
 	ttm->backup = NULL;
 }