Skip to content

Commit 034c760

Browse files
[Target] Use autogenerated getter for property
1 parent 4dab6f6 commit 034c760

File tree

1 file changed

+1
-22
lines changed

1 file changed

+1
-22
lines changed

patches/llvm-project-perf/0002-ARM-CodeGen-Disable-MEMCPY-LDM-STM-inlining-for-v7-m.patch

Lines changed: 1 addition & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -11,14 +11,6 @@ for performance gains of 1% to 2% on selected benchmarks.
1111

1212
Co-authored-by: Nashe Mncube <[email protected]>
1313
---
14-
llvm/lib/Target/ARM/ARMFeatures.td | 5 +
15-
llvm/lib/Target/ARM/ARMProcessors.td | 2 +-
16-
llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp | 121 ++++++++++++++
17-
llvm/lib/Target/ARM/ARMSelectionDAGInfo.h | 6 +
18-
llvm/lib/Target/ARM/ARMSubtarget.h | 2 +
19-
llvm/test/CodeGen/ARM/memcpy-v7m.ll | 165 ++++++++++++++++++++
20-
6 files changed, 300 insertions(+), 1 deletion(-)
21-
create mode 100644 llvm/test/CodeGen/ARM/memcpy-v7m.ll
2214

2315
diff --git a/llvm/lib/Target/ARM/ARMFeatures.td b/llvm/lib/Target/ARM/ARMFeatures.td
2416
index bb437698296c..f7fa00aba424 100644
@@ -188,7 +180,7 @@ index c57825949c1c..12db2ab1fca2 100644
188180
return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size,
189181
Alignment.value(), RTLIB::MEMCPY);
190182

191-
+ if (Subtarget.allowInlineMemcpyAsLdSt())
183+
+ if (Subtarget.useInlineMemcpyAsLdSt())
192184
+ return EmitMemcpyAsLdSt(DAG, dl, Subtarget, Chain, Dst, Src, SizeVal,
193185
+ isVolatile, DstPtrInfo, SrcPtrInfo);
194186
+
@@ -212,19 +204,6 @@ index 275b1c0f8dc0..6ff422c15b12 100644
212204
SDValue
213205
EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
214206
SDValue Dst, SDValue Src, SDValue Size,
215-
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
216-
index 2f7af05a259f..0acf919b1360 100644
217-
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
218-
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
219-
@@ -523,6 +523,8 @@ public:
220-
bool ignoreCSRForAllocationOrder(const MachineFunction &MF,
221-
unsigned PhysReg) const override;
222-
unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
223-
+
224-
+ bool allowInlineMemcpyAsLdSt() const { return UseInlineMemcpyAsLdSt; }
225-
};
226-
227-
} // end namespace llvm
228207
--
229208
2.34.1
230209

0 commit comments

Comments
 (0)