Skip to content

[Target] Use autogenerated getter for property #560

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Nov 5, 2024
Merged

[Target] Use autogenerated getter for property #560

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
23 changes: 1 addition & 22 deletions patches/llvm-project-perf/0002-ARM-CodeGen-Disable-MEMCPY-LDM-STM-inlining-for-v7-m.patch
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,14 +11,6 @@ for performance gains of 1% to 2% on selected benchmarks.

Co-authored-by: Nashe Mncube <[email protected]>
---
llvm/lib/Target/ARM/ARMFeatures.td | 5 +
llvm/lib/Target/ARM/ARMProcessors.td | 2 +-
llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp | 121 ++++++++++++++
llvm/lib/Target/ARM/ARMSelectionDAGInfo.h | 6 +
llvm/lib/Target/ARM/ARMSubtarget.h | 2 +
llvm/test/CodeGen/ARM/memcpy-v7m.ll | 165 ++++++++++++++++++++
6 files changed, 300 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/ARM/memcpy-v7m.ll

diff --git a/llvm/lib/Target/ARM/ARMFeatures.td b/llvm/lib/Target/ARM/ARMFeatures.td
index bb437698296c..f7fa00aba424 100644
Expand Down Expand Up @@ -188,7 +180,7 @@ index c57825949c1c..12db2ab1fca2 100644
return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size,
Alignment.value(), RTLIB::MEMCPY);

+ if (Subtarget.allowInlineMemcpyAsLdSt())
+ if (Subtarget.useInlineMemcpyAsLdSt())
+ return EmitMemcpyAsLdSt(DAG, dl, Subtarget, Chain, Dst, Src, SizeVal,
+ isVolatile, DstPtrInfo, SrcPtrInfo);
+
Expand All @@ -212,19 +204,6 @@ index 275b1c0f8dc0..6ff422c15b12 100644
SDValue
EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
SDValue Dst, SDValue Src, SDValue Size,
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 2f7af05a259f..0acf919b1360 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -523,6 +523,8 @@ public:
bool ignoreCSRForAllocationOrder(const MachineFunction &MF,
unsigned PhysReg) const override;
unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
+
+ bool allowInlineMemcpyAsLdSt() const { return UseInlineMemcpyAsLdSt; }
};

} // end namespace llvm
--
2.34.1

Loading