[BuildFix] Fix patch file formatting

patches/llvm-project-perf/0002-ARM-CodeGen-Disable-MEMCPY-LDM-STM-inlining-for-v7-m.patch

@@ -1,4 +1,4 @@
-From 61af6af10d10a08b81d3924fa5b35bfb548b2a05 Mon Sep 17 00:00:00 2001
+From 40f07cbde57022b25412cf1c9239755613500d86 Mon Sep 17 00:00:00 2001
 From: nasmnc01 <[email protected]>
 Author: Scott Douglass <[email protected]>
 Date: Tue, 13 Aug 2024 10:55:51 +0100
@@ -11,6 +11,11 @@ for performance gains of 1% to 2% on selected benchmarks.
 
 Co-authored-by: Nashe Mncube <[email protected]>
 ---
+ llvm/lib/Target/ARM/ARMFeatures.td          |   5 +
+ llvm/lib/Target/ARM/ARMProcessors.td        |   2 +-
+ llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp | 121 ++++++++++++++++++++
+ llvm/lib/Target/ARM/ARMSelectionDAGInfo.h   |   6 +
+ 4 files changed, 133 insertions(+), 1 deletion(-)
 
 diff --git a/llvm/lib/Target/ARM/ARMFeatures.td b/llvm/lib/Target/ARM/ARMFeatures.td
 index bb437698296c..f7fa00aba424 100644
@@ -19,14 +24,14 @@ index bb437698296c..f7fa00aba424 100644
 @@ -510,6 +510,11 @@ def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
      "DisablePostRAScheduler", "true",
      "Don't schedule again after register allocation">;
-
+ 
 +def FeatureUseInlineMemcpyAsLdSt :
 +    SubtargetFeature<"use-inline-memcpy-ldst", "UseInlineMemcpyAsLdSt",
 +        "true", "Use memcpy inlining as LD/ST instructions">;
 +
 +
  // Armv8.5-A extensions
-
+ 
  // Has speculation barrier.
 diff --git a/llvm/lib/Target/ARM/ARMProcessors.td b/llvm/lib/Target/ARM/ARMProcessors.td
 index b94a5fc16146..ffb0c86bc687 100644
@@ -38,15 +43,15 @@ index b94a5fc16146..ffb0c86bc687 100644
  def ProcM7      : SubtargetFeature<"m7", "ARMProcFamily", "CortexM7",
 -                                   "Cortex-M7 ARM processors", []>;
 +                                   "Cortex-M7 ARM processors", [FeatureUseInlineMemcpyAsLdSt]>;
-
+ 
  //===----------------------------------------------------------------------===//
  // ARM processors
 diff --git a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
-index c57825949c1c..12db2ab1fca2 100644
+index c57825949c1c..63ae7a042886 100644
 --- a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
 +++ b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
 @@ -12,6 +12,7 @@
-
+ 
  #include "ARMTargetMachine.h"
  #include "ARMTargetTransformInfo.h"
 +#include "llvm/ADT/SmallVector.h"
@@ -56,7 +61,7 @@ index c57825949c1c..12db2ab1fca2 100644
 @@ -138,6 +139,122 @@ SDValue ARMSelectionDAGInfo::EmitSpecializedLibcall(
    return CallResult.second;
  }
-
+ 
 +SDValue ARMSelectionDAGInfo::EmitMemcpyAsLdSt(
 +    SelectionDAG &DAG, SDLoc dl, const ARMSubtarget &Subtarget, SDValue Chain,
 +    SDValue Dst, SDValue Src, uint64_t SizeVal, bool isVolatile,
@@ -179,7 +184,7 @@ index c57825949c1c..12db2ab1fca2 100644
 @@ -192,6 +309,10 @@ SDValue ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(
      return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size,
                                    Alignment.value(), RTLIB::MEMCPY);
-
+ 
 +  if (Subtarget.useInlineMemcpyAsLdSt())
 +    return EmitMemcpyAsLdSt(DAG, dl, Subtarget, Chain, Dst, Src, SizeVal,
 +                            isVolatile, DstPtrInfo, SrcPtrInfo);
@@ -194,7 +199,7 @@ index 275b1c0f8dc0..6ff422c15b12 100644
 @@ -44,6 +44,12 @@ public:
                                    MachinePointerInfo DstPtrInfo,
                                    MachinePointerInfo SrcPtrInfo) const override;
-
+ 
 +  SDValue EmitMemcpyAsLdSt(SelectionDAG &DAG, SDLoc dl,
 +                           const ARMSubtarget &Subtarget, SDValue Chain,
 +                           SDValue Dst, SDValue Src, uint64_t SizeVal,
@@ -204,6 +209,6 @@ index 275b1c0f8dc0..6ff422c15b12 100644
    SDValue
    EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
                             SDValue Dst, SDValue Src, SDValue Size,
---
+-- 
 2.34.1