Add support for the Brain 16-bit floating-point vector multiplication (FEAT_SVE_BFSCALE) intrinsics #410
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LGTM other than the extra new line |
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Should this also be added as an alpha specification, like you did for the Multiplication of modal 8-bit floating-point matrices
… intrinsics Adds intrinsic support for the Brain 16-bit floating-point vector multiplication instructions introduced by the FEAT_SVE_BFSCALE feature in 2024 dpISA. BFSCALE: BFloat16 adjust exponent by vector (predicated) BFSCALE (multiple and single vector): Multi-vector BFloat16 adjust exponent by vector BFSCALE (multiple vectors): Multi-vector BFloat16 adjust exponent BFMUL (multiple and single vector): Multi-vector BFloat16 floating-point multiply by vector BFMUL (multiple vectors): Multi-vector BFloat16 floating-point multiply
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…ns (#163346) This patch add intrinsics support for multi-vector BFMUL and BFSCALE instruction based on [this](ARM-software/acle#410) ACLE specification proposal
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… instructions (#163346) This patch add intrinsics support for multi-vector BFMUL and BFSCALE instruction based on [this](ARM-software/acle#410) ACLE specification proposal
| uint64_t imm_idx); | ||
| ``` | ||
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| ### SVE2 BFloat16 floating-point adjust exponent vectors instructions. |
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Can we change this to SVE instead of SVE2?
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| ``` c | ||
| // Only if __ARM_FEATURE_SVE_BFSCALE != 0 | ||
| svbfloat16x2_t svscale[_bf16_x2](svbfloat16x2_t zdn, svint16x2_t zm); |
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Are these sme instructions? Should it also be followed by: __arm_streaming;
Kmeakin
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Nov 12, 2025
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| ``` c | ||
| // Only if __ARM_FEATURE_SVE_BFSCALE != 0 | ||
| svbfloat16_t svscale[_bf16]_m (svbool_t pg, svbfloat16_t zdn, svbfloat16_t zm); |
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I think the last argument to all these functions should be a svint16_t since the corresponding instruction scales by an integer, not a float
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