Skip to content

chapter3: raise RISC-V SBI requirement #147

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
xypron wants to merge 1 commit into from
Closed

chapter3: raise RISC-V SBI requirement #147

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 6 additions & 2 deletions source/chapter3-secureworld.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -60,5 +60,9 @@ RISC-V Multiprocessor Startup Protocol
======================================

The resident firmware in M mode or hypervisor running in HS mode must implement
and conform to at least SBI [RVSBISPEC]_ v0.2 with HART State Management(HSM)
extension for both RV32 and RV64.
and conform to at least SBI [RVSBISPEC]_ v2.0 with at least these extensions:

* Base Extension
* HART State Management Extension (HSM)
* System Reset Extension (SRST)
* Debug Console Extension (DBCN) if a serial console is present