STM32G0: introduce sub family for custom boards

STM32G030x8
STM32G041x8
STM32G050x8
STM32G051x8
STM32G061x8
STM32G081xB
STM32G0B0xE
STM32G0B1xE
STM32G0C1xE

Author: jeromecoutant

targets/TARGET_STM/TARGET_STM32G0/CMakeLists.txt

@@ -4,9 +4,17 @@
 add_subdirectory(TARGET_STM32G030x8 EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_STM32G031x8 EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_STM32G041x8 EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_STM32G050x8 EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_STM32G051x8 EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_STM32G061x8 EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_STM32G070xB EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_STM32G071xB EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_STM32G081xB EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_STM32G0B0xE EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_STM32G0B1xE EXCLUDE_FROM_ALL)
+
+add_subdirectory(TARGET_STM32G0C1xE EXCLUDE_FROM_ALL)
+
 add_subdirectory(STM32Cube_FW EXCLUDE_FROM_ALL)
 
 add_library(mbed-stm32g0 INTERFACE)

targets/TARGET_STM/TARGET_STM32G0/PeripheralNames.h

@@ -22,12 +22,12 @@ extern "C" {
 #endif
 
 typedef enum {
-    ADC_1 = (int)ADC1_BASE
+    ADC_1 = (int)ADC1_BASE,
 } ADCName;
 
 #if defined DAC_BASE
 typedef enum {
-    DAC_1 = (int)DAC_BASE
+    DAC_1 = (int)DAC_BASE,
 } DACName;
 #endif
 
@@ -40,32 +40,69 @@ typedef enum {
 #if defined USART4_BASE
     UART_4   = (int)USART4_BASE,
 #endif
-    LPUART_1 = (int)LPUART1_BASE
+#if defined USART5_BASE
+    UART_5   = (int)USART5_BASE,
+#endif
+#if defined USART6_BASE
+    UART_6   = (int)USART6_BASE,
+#endif
+#if defined LPUART1_BASE
+    LPUART_1 = (int)LPUART1_BASE,
+#endif
+#if defined LPUART2_BASE
+    LPUART_2 = (int)LPUART2_BASE,
+#endif
 } UARTName;
 
 #define DEVICE_SPI_COUNT 2
 typedef enum {
     SPI_1 = (int)SPI1_BASE,
-    SPI_2 = (int)SPI2_BASE
+    SPI_2 = (int)SPI2_BASE,
+#if defined SPI3_BASE
+    SPI_3 = (int)SPI3_BASE,
+#endif
 } SPIName;
 
 typedef enum {
     I2C_1 = (int)I2C1_BASE,
-    I2C_2 = (int)I2C2_BASE
+    I2C_2 = (int)I2C2_BASE,
+#if defined I2C3_BASE
+    I2C_3 = (int)I2C3_BASE,
+#endif
 } I2CName;
 
 typedef enum {
     PWM_1  = (int)TIM1_BASE,
+#if defined TIM2_BASE
     PWM_2  = (int)TIM2_BASE,
+#endif
     PWM_3  = (int)TIM3_BASE,
+#if defined TIM4_BASE
+    PWM_4  = (int)TIM4_BASE,
+#endif
     PWM_14 = (int)TIM14_BASE,
 #if defined TIM15_BASE
     PWM_15 = (int)TIM15_BASE,
 #endif
     PWM_16 = (int)TIM16_BASE,
-    PWM_17 = (int)TIM17_BASE
+    PWM_17 = (int)TIM17_BASE,
 } PWMName;
 
+#if defined FDCAN1_BASE
+typedef enum {
+    CAN_1 = (int)FDCAN1_BASE,
+#if defined FDCAN2_BASE
+    CAN_2 = (int)FDCAN2_BASE,
+#endif
+} CANName;
+#endif
+
+#if defined USB_BASE
+typedef enum {
+    USB_FS = (int)USB_BASE
+} USBName;
+#endif
+
 #ifdef __cplusplus
 }
 #endif

targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/CMakeLists.txt

@@ -0,0 +1,26 @@
+# Copyright (c) 2020 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
+    set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g050xx.S)
+    set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g050x8.ld)
+elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
+    set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g050xx.S)
+    set(LINKER_FILE TOOLCHAIN_ARM/stm32g050x8.sct)
+endif()
+
+add_library(mbed-stm32g050x8 INTERFACE)
+
+target_include_directories(mbed-stm32g050x8
+    INTERFACE
+        .
+)
+
+target_sources(mbed-stm32g050x8
+    INTERFACE
+        ${STARTUP_FILE}
+)
+
+mbed_set_linker_script(mbed-stm32g050x8 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
+
+target_link_libraries(mbed-stm32g050x8 INTERFACE mbed-stm32g0)

targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_ARM/startup_stm32g050xx.S

@@ -0,0 +1,194 @@
+;******************************************************************************
+;* File Name          : startup_stm32g050xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32G050xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM0 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2018-2021 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;******************************************************************************
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
+__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit|                   ; Top of Stack
+                DCD     Reset_Handler                  ; Reset Handler
+                DCD     NMI_Handler                    ; NMI Handler
+                DCD     HardFault_Handler              ; Hard Fault Handler
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     SVC_Handler                    ; SVCall Handler
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     PendSV_Handler                 ; PendSV Handler
+                DCD     SysTick_Handler                ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                ; Window Watchdog
+                DCD     0                              ; Reserved
+                DCD     RTC_TAMP_IRQHandler            ; RTC through EXTI Line
+                DCD     FLASH_IRQHandler               ; FLASH
+                DCD     RCC_IRQHandler                 ; RCC
+                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
+                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
+                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
+                DCD     0                              ; Reserved
+                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
+                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
+                DCD     DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMAMUX1 overrun
+                DCD     ADC1_IRQHandler                ; ADC1
+                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
+                DCD     0                              ; Reserved
+                DCD     TIM3_IRQHandler                ; TIM3
+                DCD     TIM6_IRQHandler                ; TIM6
+                DCD     TIM7_IRQHandler                ; TIM7
+                DCD     TIM14_IRQHandler               ; TIM14
+                DCD     TIM15_IRQHandler               ; TIM15
+                DCD     TIM16_IRQHandler               ; TIM16
+                DCD     TIM17_IRQHandler               ; TIM17
+                DCD     I2C1_IRQHandler                ; I2C1
+                DCD     I2C2_IRQHandler                ; I2C2
+                DCD     SPI1_IRQHandler                ; SPI1
+                DCD     SPI2_IRQHandler                ; SPI2
+                DCD     USART1_IRQHandler              ; USART1
+                DCD     USART2_IRQHandler              ; USART2
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  __main
+        IMPORT  SystemInit  
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                [WEAK]
+                EXPORT  RTC_TAMP_IRQHandler            [WEAK]
+                EXPORT  FLASH_IRQHandler               [WEAK]
+                EXPORT  RCC_IRQHandler                 [WEAK]
+                EXPORT  EXTI0_1_IRQHandler             [WEAK]
+                EXPORT  EXTI2_3_IRQHandler             [WEAK]
+                EXPORT  EXTI4_15_IRQHandler            [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
+                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
+                EXPORT  DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler [WEAK]
+                EXPORT  ADC1_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+                EXPORT  TIM1_CC_IRQHandler             [WEAK]
+                EXPORT  TIM3_IRQHandler                [WEAK]
+                EXPORT  TIM6_IRQHandler                [WEAK]
+                EXPORT  TIM7_IRQHandler                [WEAK]
+                EXPORT  TIM14_IRQHandler               [WEAK]
+                EXPORT  TIM15_IRQHandler               [WEAK]
+                EXPORT  TIM16_IRQHandler               [WEAK]
+                EXPORT  TIM17_IRQHandler               [WEAK]
+                EXPORT  I2C1_IRQHandler                [WEAK]
+                EXPORT  I2C2_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                [WEAK]
+                EXPORT  SPI2_IRQHandler                [WEAK]
+                EXPORT  USART1_IRQHandler              [WEAK]
+                EXPORT  USART2_IRQHandler              [WEAK]
+
+
+WWDG_IRQHandler
+RTC_TAMP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
+ADC1_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM3_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_ARM/stm32g050x8.sct

@@ -0,0 +1,57 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; Scatter-Loading Description File
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016-2020 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+#include "../cmsis_nvic.h"
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START  MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE  MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
+#if defined(MBED_BOOT_STACK_SIZE)
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
+#else
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE  (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
+
+LR_IROM1  MBED_APP_START  MBED_APP_SIZE  {
+
+  ER_IROM1  MBED_APP_START  MBED_APP_SIZE  {
+    *.o (RESET, +First)
+    *(InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+  RW_IRAM1  (MBED_RAM_START + VECTORS_SIZE)  {  ; RW data
+    .ANY (+RW +ZI)
+  }
+
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))  { ; Heap growing up
+  }
+
+  ARM_LIB_STACK  (MBED_RAM_START + MBED_RAM_SIZE)  EMPTY  -MBED_CONF_TARGET_BOOT_STACK_SIZE  { ; Stack region growing down
+  }
+}