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SystemCoreClock should correspond to current core clock and not D1 clock.
1 parent adcf0e2 commit 48aba33

16 files changed

+68
-90
lines changed

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_stm32h7xx.c

Lines changed: 24 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,8 @@
1717
* by the user application to setup the SysTick
1818
* timer or configure other parameters.
1919
*
20-
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
21-
* be called whenever the core clock is changed
20+
* - SystemCoreClockUpdate(): Updates the variables SystemD1Clock and SystemD2Clock
21+
* and must be called whenever the core clock is changed
2222
* during program execution.
2323
*
2424
*
@@ -111,7 +111,14 @@
111111
is no need to call the 2 first functions listed above, since SystemCoreClock
112112
variable is updated automatically.
113113
*/
114-
uint32_t SystemCoreClock = 64000000;
114+
#if defined(CORE_CM7)
115+
#define SystemCoreClock SystemD1Clock
116+
#elif defined(CORE_CM4)
117+
#define SystemCoreClock SystemD2Clock
118+
#else
119+
#error "Wrong core selection"
120+
#endif
121+
uint32_t SystemD1Clock = 64000000;
115122
uint32_t SystemD2Clock = 64000000;
116123
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
117124

@@ -237,7 +244,7 @@ void SystemInit (void)
237244
}
238245

239246
/**
240-
* @brief Update SystemCoreClock variable according to Clock Register Values.
247+
* @brief Update SystemD1Clock and SystemD2Clock variables according to Clock Register Values.
241248
* The SystemCoreClock variable contains the core clock , it can
242249
* be used by the user application to setup the SysTick timer or configure
243250
* other parameters.
@@ -250,10 +257,10 @@ void SystemInit (void)
250257
* frequency in the chip. It is calculated based on the predefined
251258
* constant and the selected clock source:
252259
*
253-
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
254-
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
255-
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
256-
* - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
260+
* - If SYSCLK source is CSI, SystemD1Clock will contain the CSI_VALUE(*)
261+
* - If SYSCLK source is HSI, SystemD1Clock will contain the HSI_VALUE(**)
262+
* - If SYSCLK source is HSE, SystemD1Clock will contain the HSE_VALUE(***)
263+
* - If SYSCLK source is PLL, SystemD1Clock will contain the CSI_VALUE(*),
257264
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
258265
*
259266
* (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
@@ -283,16 +290,16 @@ void SystemCoreClockUpdate (void)
283290
switch (RCC->CFGR & RCC_CFGR_SWS)
284291
{
285292
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
286-
SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
293+
SystemD1Clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
287294

288295
break;
289296

290297
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
291-
SystemCoreClock = CSI_VALUE;
298+
SystemD1Clock = CSI_VALUE;
292299
break;
293300

294301
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
295-
SystemCoreClock = HSE_VALUE;
302+
SystemD1Clock = HSE_VALUE;
296303
break;
297304

298305
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
@@ -329,27 +336,27 @@ void SystemCoreClockUpdate (void)
329336
break;
330337
}
331338
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
332-
SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
339+
SystemD1Clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
333340
}
334341
else
335342
{
336-
SystemCoreClock = 0U;
343+
SystemD1Clock = 0U;
337344
}
338345
break;
339346

340347
default:
341-
SystemCoreClock = CSI_VALUE;
348+
SystemD1Clock = CSI_VALUE;
342349
break;
343350
}
344351

345352
/* Compute SystemClock frequency --------------------------------------------------*/
346353
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
347354

348-
/* SystemCoreClock frequency : CM7 CPU frequency */
349-
SystemCoreClock >>= tmp;
355+
/* SystemD1Clock frequency : CM7 CPU frequency */
356+
SystemD1Clock >>= tmp;
350357

351358
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
352-
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
359+
SystemD2Clock = (SystemD1Clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
353360

354361
}
355362

‎targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.c

Lines changed: 2 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -145,10 +145,10 @@ HAL_StatusTypeDef HAL_Init(void)
145145
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
146146

147147
/* Update the SystemCoreClock global variable */
148-
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
148+
SystemD1Clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
149149

150150
/* Update the SystemD2Clock global variable */
151-
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
151+
SystemD2Clock = (SystemD1Clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
152152

153153
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
154154
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
@@ -251,32 +251,11 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
251251
return HAL_ERROR;
252252
}
253253

254-
#if defined(DUAL_CORE)
255-
if (HAL_GetCurrentCPUID() == CM7_CPUID)
256-
{
257-
/* Cortex-M7 detected */
258-
/* Configure the SysTick to have interrupt in 1ms time basis*/
259-
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
260-
{
261-
return HAL_ERROR;
262-
}
263-
}
264-
else
265-
{
266-
/* Cortex-M4 detected */
267-
/* Configure the SysTick to have interrupt in 1ms time basis*/
268-
if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000UL / (uint32_t)uwTickFreq)) > 0U)
269-
{
270-
return HAL_ERROR;
271-
}
272-
}
273-
#else
274254
/* Configure the SysTick to have interrupt in 1ms time basis*/
275255
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
276256
{
277257
return HAL_ERROR;
278258
}
279-
#endif
280259

281260
/* Configure the SysTick IRQ priority */
282261
if (TickPriority < (1UL << __NVIC_PRIO_BITS))

‎targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -500,7 +500,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
500500
/* Note: Variable divided by 2 to compensate partially */
501501
/* CPU processing cycles, scaling in us split to not */
502502
/* exceed 32 bits register capacity and handle low frequency. */
503-
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
503+
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemD1Clock / (100000UL * 2UL)));
504504
while (wait_loop_index != 0UL)
505505
{
506506
wait_loop_index--;
@@ -2804,7 +2804,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
28042804
/* Note: Variable divided by 2 to compensate partially */
28052805
/* CPU processing cycles, scaling in us split to not */
28062806
/* exceed 32 bits register capacity and handle low frequency. */
2807-
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
2807+
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemD1Clock / (100000UL * 2UL)));
28082808
while(wait_loop_index != 0UL)
28092809
{
28102810
wait_loop_index--;

‎targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -335,7 +335,7 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc,
335335
/* Wait loop initialization and execution */
336336
/* Note: Variable divided by 2 to compensate partially */
337337
/* CPU processing cycles. */
338-
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000UL * 2UL)));
338+
wait_loop_index = (ADC_STAB_DELAY_US * (SystemD1Clock / (1000000UL * 2UL)));
339339
while(wait_loop_index != 0UL)
340340
{
341341
wait_loop_index--;
@@ -2122,7 +2122,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
21222122
/* Note: Variable divided by 2 to compensate partially */
21232123
/* CPU processing cycles, scaling in us split to not */
21242124
/* exceed 32 bits register capacity and handle low frequency. */
2125-
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
2125+
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemD1Clock / (100000UL * 2UL)));
21262126
while(wait_loop_index != 0UL)
21272127
{
21282128
wait_loop_index--;

‎targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_comp.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
364364
/* Note: Variable divided by 2 to compensate partially */
365365
/* CPU processing cycles.*/
366366

367-
wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000UL * 2UL)));
367+
wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemD1Clock / (1000000UL * 2UL)));
368368

369369
while(wait_loop_index != 0UL)
370370
{
@@ -743,7 +743,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
743743
/* Note: Variable divided by 2 to compensate partially */
744744
/* CPU processing cycles. */
745745

746-
wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL)));
746+
wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemD1Clock / (1000000UL * 2UL)));
747747
while(wait_loop_index != 0UL)
748748
{
749749
wait_loop_index--;
@@ -840,7 +840,7 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
840840
/* Note: Variable divided by 2 to compensate partially */
841841
/* CPU processing cycles. */
842842

843-
wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL)));
843+
wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemD1Clock / (1000000UL * 2UL)));
844844
while(wait_loop_index != 0UL)
845845
{
846846
wait_loop_index--;

‎targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dcmi.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -643,7 +643,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
643643
*/
644644
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
645645
{
646-
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8U/1000U);
646+
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * ( SystemD1Clock/8U/1000U);
647647
HAL_StatusTypeDef status = HAL_OK;
648648

649649
/* Process locked */
@@ -697,7 +697,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
697697
*/
698698
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
699699
{
700-
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8U/1000U);
700+
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * ( SystemD1Clock/8U/1000U);
701701
HAL_StatusTypeDef status = HAL_OK;
702702

703703
/* Process locked */

‎targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dma.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1150,7 +1150,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
11501150
uint32_t tmpisr_dma, tmpisr_bdma;
11511151
uint32_t ccr_reg;
11521152
__IO uint32_t count = 0U;
1153-
uint32_t timeout = SystemCoreClock / 9600U;
1153+
uint32_t timeout = SystemD1Clock / 9600U;
11541154

11551155
/* calculate DMA base and stream number */
11561156
DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;

‎targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mdma.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1512,7 +1512,7 @@ HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma)
15121512
void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma)
15131513
{
15141514
__IO uint32_t count = 0;
1515-
uint32_t timeout = SystemCoreClock / 9600U;
1515+
uint32_t timeout = SystemD1Clock / 9600U;
15161516

15171517
uint32_t generalIntFlag, errorFlag;
15181518

‎targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -210,8 +210,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
210210
/* Reset CFGR register */
211211
CLEAR_REG(RCC->CFGR);
212212

213-
/* Update the SystemCoreClock global variable */
214-
SystemCoreClock = HSI_VALUE;
213+
/* Update the SystemD1Clock global variable */
214+
SystemD1Clock = HSI_VALUE;
215215

216216
/* Adapt Systick interrupt period */
217217
if(HAL_InitTick(uwTickPrio) != HAL_OK)
@@ -1044,8 +1044,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
10441044
}
10451045
}
10461046

1047-
/* Update the SystemCoreClock global variable */
1048-
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
1047+
/* Update the SystemD1Clock global variable */
1048+
SystemD1Clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
10491049

10501050
/* Configure the source of time base considering new system clocks settings*/
10511051
halstatus = HAL_InitTick (uwTickPrio);

‎targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc_ex.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2188,8 +2188,8 @@ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
21882188
*/
21892189
uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
21902190
{
2191-
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
2192-
return SystemCoreClock;
2191+
SystemD1Clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
2192+
return SystemD1Clock;
21932193
}
21942194

21952195
/**

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