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musca_b1: Add TF-M compatibility
Make the MUSCA_B1 target TF-M compatible by doing the following: - Add flash, region definitions, and preprocessed image macros from TF-M (at version 6e7be077eabe "Core: Add lifecycle API") - Update the MUSCA_B1 linker script to create a flash image compatible with TF-M. - Update the tfm/bin_utils/assemble.py signing script to work with preprocessed image macros rather than flat C pre-processor defines Signed-off-by: Devaraj Ranganna <[email protected]> Signed-off-by: Jaeden Amero <[email protected]>
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7 files changed

+303
-163
lines changed

7 files changed

+303
-163
lines changed

‎targets/TARGET_ARM_SSG/TARGET_MUSCA_B1/device/TOOLCHAIN_GCC_ARM/musca_ns.ld

Lines changed: 29 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@
3232

3333
MEMORY
3434
{
35-
CODE_RAM (rx) : ORIGIN = NS_CODE_START, LENGTH = ((TOTAL_CODE_SRAM_SIZE / 2) - BL2_HEADER_SIZE)
35+
FLASH (rx) : ORIGIN = NS_CODE_START, LENGTH = NS_CODE_SIZE
3636
/* Vector table is copied to RAM, so RAM address needs to be adjusted */
3737
RAM (rwx) : ORIGIN = NVIC_RAM_VECTOR_LIMIT, LENGTH = (NS_DATA_SIZE - NVIC_RAM_VECTOR_SIZE)
3838
}
@@ -46,38 +46,17 @@ ENTRY(Reset_Handler)
4646

4747
SECTIONS
4848
{
49-
/* Startup section is loaded to Flash and runs from Flash */
50-
.startup :
49+
.text :
5150
{
5251
KEEP(*(.vectors))
5352
__Vectors_End = .;
5453
__Vectors_Size = __Vectors_End - __Vectors;
5554
__end__ = .;
5655

56+
*(.text*)
5757
KEEP(*(.init))
5858
KEEP(*(.fini))
5959

60-
} > CODE_RAM
61-
62-
.ARM.extab :
63-
{
64-
*(.ARM.extab* .gnu.linkonce.armextab.*)
65-
} > CODE_RAM
66-
67-
__exidx_start = .;
68-
.ARM.exidx :
69-
{
70-
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
71-
} > CODE_RAM
72-
__exidx_end = .;
73-
74-
/* The text section is loaded into Flash but runs from SRAM
75-
* The load address is aligned to 8 bytes
76-
*/
77-
.text : ALIGN(8)
78-
{
79-
*(.text*)
80-
8160
/* .ctors */
8261
*crtbegin.o(.ctors)
8362
*crtbegin?.o(.ctors)
@@ -95,25 +74,26 @@ SECTIONS
9574
*(.rodata*)
9675

9776
KEEP(*(.eh_frame*))
98-
} >CODE_RAM
99-
. = ALIGN(8); /* This alignment is needed to make the section size 8 bytes aligned */
100-
101-
/* Create same symbols that armclang does so that in the c files
102-
* we do not have to deal with the compiler type
103-
*/
104-
Image$$ER_CODE_SRAM$$Base = ADDR(.text);
105-
Image$$ER_CODE_SRAM$$Limit = .;
106-
Image$$ER_CODE_SRAM$$Length = Image$$ER_CODE_SRAM$$Limit - Image$$ER_CODE_SRAM$$Base;
107-
Load$$ER_CODE_SRAM$$Base = LOADADDR(.text);
108-
Load$$ER_CODE_SRAM$$Length = Image$$ER_CODE_SRAM$$Length;
109-
Load$$ER_CODE_SRAM$$Limit = Load$$ER_CODE_SRAM$$Base + Load$$ER_CODE_SRAM$$Length;
77+
} > FLASH
78+
79+
.ARM.extab :
80+
{
81+
*(.ARM.extab* .gnu.linkonce.armextab.*)
82+
} > FLASH
83+
84+
__exidx_start = .;
85+
.ARM.exidx :
86+
{
87+
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
88+
} > FLASH
89+
__exidx_end = .;
11090

11191
/* To copy multiple ROM to RAM sections,
11292
* define etext2/data2_start/data2_end and
11393
* define __STARTUP_COPY_MULTIPLE in startup_cmsdk_musca_ns.S */
11494
.copy.table :
11595
{
116-
. = ALIGN(8);
96+
. = ALIGN(4);
11797
__copy_table_start__ = .;
11898
LONG (__etext)
11999
LONG (__data_start__)
@@ -122,64 +102,65 @@ SECTIONS
122102
LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
123103
LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0)
124104
__copy_table_end__ = .;
125-
} > CODE_RAM
105+
} > FLASH
126106

127107
/* To clear multiple BSS sections,
108+
* uncomment .zero.table section and,
128109
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_cmsdk_musca_ns.S */
129110
.zero.table :
130111
{
131-
. = ALIGN(8);
112+
. = ALIGN(4);
132113
__zero_table_start__ = .;
133114
LONG (__bss_start__)
134115
LONG (__bss_end__ - __bss_start__)
135116
LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
136117
LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0)
137118
__zero_table_end__ = .;
138-
} > CODE_RAM
119+
} > FLASH
139120

140121
__etext = .;
141122

142-
.data : ALIGN(8)
123+
.data : AT (__etext)
143124
{
144125
__data_start__ = .;
145126
*(vtable)
146127
*(.data*)
147128

148-
. = ALIGN(8);
129+
. = ALIGN(4);
149130
/* preinit data */
150131
PROVIDE_HIDDEN (__preinit_array_start = .);
151132
KEEP(*(.preinit_array))
152133
PROVIDE_HIDDEN (__preinit_array_end = .);
153134

154-
. = ALIGN(8);
135+
. = ALIGN(4);
155136
/* init data */
156137
PROVIDE_HIDDEN (__init_array_start = .);
157138
KEEP(*(SORT(.init_array.*)))
158139
KEEP(*(.init_array))
159140
PROVIDE_HIDDEN (__init_array_end = .);
160141

161142

162-
. = ALIGN(8);
143+
. = ALIGN(4);
163144
/* finit data */
164145
PROVIDE_HIDDEN (__fini_array_start = .);
165146
KEEP(*(SORT(.fini_array.*)))
166147
KEEP(*(.fini_array))
167148
PROVIDE_HIDDEN (__fini_array_end = .);
168149

169150
KEEP(*(.jcr*))
170-
. = ALIGN(8);
151+
. = ALIGN(4);
171152
/* All data end */
172153
__data_end__ = .;
173154

174-
} > RAM AT>CODE_RAM
155+
} > RAM
175156

176157
.bss :
177158
{
178-
. = ALIGN(8);
159+
. = ALIGN(4);
179160
__bss_start__ = .;
180161
*(.bss*)
181162
*(COMMON)
182-
. = ALIGN(8);
163+
. = ALIGN(4);
183164
__bss_end__ = .;
184165
} > RAM
185166

‎targets/TARGET_ARM_SSG/TARGET_MUSCA_B1/device/device_cfg.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,6 @@
8787
#define USEC_REPORTED_FREQ_HZ (TIMER_FREQ_HZ >> USEC_REPORTED_SHIFT)
8888
#define USEC_REPORTED_BITS (32 - USEC_REPORTED_SHIFT)
8989

90-
#define UART_DEFAULT_BAUD_RATE 9600U
90+
#define DEFAULT_UART_BAUDRATE 9600U
9191

9292
#endif /* __ARM_LTD_DEVICE_CFG_H__ */

‎targets/TARGET_ARM_SSG/TARGET_MUSCA_B1/device/device_definition.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -298,7 +298,7 @@ struct gpio_cmsdk_dev_t GPIO0_CMSDK_DEV_S = {&(GPIO0_CMSDK_DEV_CFG_S)};
298298
#ifdef UART0_PL011_S
299299
static const struct uart_pl011_dev_cfg_t UART0_PL011_DEV_CFG_S = {
300300
.base = MUSCA_B1_UART0_S_BASE,
301-
.def_baudrate = UART_DEFAULT_BAUD_RATE,
301+
.def_baudrate = DEFAULT_UART_BAUDRATE,
302302
.def_wlen = UART_PL011_WLEN_8,
303303
.def_parity = UART_PL011_PARITY_DISABLED,
304304
.def_stopbit = UART_PL011_STOPBIT_1};
@@ -312,7 +312,7 @@ struct uart_pl011_dev_t UART0_PL011_DEV_S = {&(UART0_PL011_DEV_CFG_S),
312312
#ifdef UART0_PL011_NS
313313
static const struct uart_pl011_dev_cfg_t UART0_PL011_DEV_CFG_NS = {
314314
.base = MUSCA_B1_UART0_NS_BASE,
315-
.def_baudrate = UART_DEFAULT_BAUD_RATE,
315+
.def_baudrate = DEFAULT_UART_BAUDRATE,
316316
.def_wlen = UART_PL011_WLEN_8,
317317
.def_parity = UART_PL011_PARITY_DISABLED,
318318
.def_stopbit = UART_PL011_STOPBIT_1};
@@ -327,7 +327,7 @@ struct uart_pl011_dev_t UART0_PL011_DEV_NS = {&(UART0_PL011_DEV_CFG_NS),
327327
#ifdef UART1_PL011_S
328328
static const struct uart_pl011_dev_cfg_t UART1_PL011_DEV_CFG_S = {
329329
.base = MUSCA_B1_UART1_S_BASE,
330-
.def_baudrate = UART_DEFAULT_BAUD_RATE,
330+
.def_baudrate = DEFAULT_UART_BAUDRATE,
331331
.def_wlen = UART_PL011_WLEN_8,
332332
.def_parity = UART_PL011_PARITY_DISABLED,
333333
.def_stopbit = UART_PL011_STOPBIT_1};
@@ -341,7 +341,7 @@ struct uart_pl011_dev_t UART1_PL011_DEV_S = {&(UART1_PL011_DEV_CFG_S),
341341
#ifdef UART1_PL011_NS
342342
static const struct uart_pl011_dev_cfg_t UART1_PL011_DEV_CFG_NS = {
343343
.base = MUSCA_B1_UART1_NS_BASE,
344-
.def_baudrate = UART_DEFAULT_BAUD_RATE,
344+
.def_baudrate = DEFAULT_UART_BAUDRATE,
345345
.def_wlen = UART_PL011_WLEN_8,
346346
.def_parity = UART_PL011_PARITY_DISABLED,
347347
.def_stopbit = UART_PL011_STOPBIT_1};

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