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[NUCLEO_L152RE] Fix bugs with gpio and serial
1 parent cbfdc4e commit ba5866b

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9 files changed

+70
-198
lines changed

9 files changed

+70
-198
lines changed

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx.sct

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -27,21 +27,16 @@
2727
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2828
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2929

30-
; STM32L152RE: 512KB FLASH (0x80000) + 80KB RAM (0x14000)
31-
; STM32L152RC: 256KB FLASH (0x40000) + 32KB RAM (0x08000)
30+
LR_IROM1 0x08000000 0x80000 { ; load region size_region (512 KB)
3231

33-
;LR_IROM1 0x08000000 0x80000 { ; load region size_region
34-
LR_IROM1 0x08000000 0x40000 { ; load region size_region
35-
; ER_IROM1 0x08000000 0x80000 { ; load address = execution address
36-
ER_IROM1 0x08000000 0x40000 { ; load address = execution address
32+
ER_IROM1 0x08000000 0x80000 { ; load address = execution address
3733
*.o (RESET, +First)
3834
*(InRoot$$Sections)
3935
.ANY (+RO)
4036
}
4137

4238
; 73 vectors = 292 bytes (0x124) to be reserved in RAM
43-
; RW_IRAM1 (0x20000000+0x124) (0x14000-0x124) { ; RW data
44-
RW_IRAM1 (0x20000000+0x124) (0x08000-0x124) { ; RW data
39+
RW_IRAM1 (0x20000000+0x124) (0x14000-0x124) { ; RW data
4540
.ANY (+RW +ZI)
4641
}
4742

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/system_stm32l1xx.c

Lines changed: 8 additions & 146 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
* @file system_stm32l1xx.c
44
* @author MCD Application Team
55
* @version V1.2.0
6-
* @date 8-January-2014
6+
* @date 11-January-2014
77
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
88
* This file contains the system clock configuration for STM32L1xx Ultra
99
* Low power devices, and is generated by the clock configuration
@@ -47,9 +47,9 @@
4747
*-----------------------------------------------------------------------------
4848
* SYSCLK | 16000000 Hz
4949
*-----------------------------------------------------------------------------
50-
* HCLK | 8000000 Hz
50+
* HCLK | 16000000 Hz
5151
*-----------------------------------------------------------------------------
52-
* AHB Prescaler | 2
52+
* AHB Prescaler | 1
5353
*-----------------------------------------------------------------------------
5454
* APB1 Prescaler | 1
5555
*-----------------------------------------------------------------------------
@@ -63,12 +63,10 @@
6363
*-----------------------------------------------------------------------------
6464
* VDD | 3.3 V
6565
*-----------------------------------------------------------------------------
66-
* Vcore | 1.5 V (Range 2)
66+
* Vcore | 1.8 V (Range 1)
6767
*-----------------------------------------------------------------------------
6868
* Flash Latency | 0 WS
6969
*-----------------------------------------------------------------------------
70-
* SDIO clock (SDIOCLK) | NA
71-
*-----------------------------------------------------------------------------
7270
* Require 48MHz for USB clock | Disabled
7371
*-----------------------------------------------------------------------------
7472
*=============================================================================
@@ -121,10 +119,6 @@
121119
* @{
122120
*/
123121

124-
/*!< Uncomment the following line if you need to use external SRAM mounted
125-
on STM32L152D_EVAL board as data memory */
126-
/* #define DATA_IN_ExtSRAM */
127-
128122
/*!< Uncomment the following line if you need to relocate your vector Table in
129123
Internal SRAM. */
130124
/* #define VECT_TAB_SRAM */
@@ -158,9 +152,6 @@ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
158152
*/
159153

160154
static void SetSysClock(void);
161-
#ifdef DATA_IN_ExtSRAM
162-
static void SystemInit_ExtMemCtl(void);
163-
#endif /* DATA_IN_ExtSRAM */
164155

165156
/**
166157
* @}
@@ -196,10 +187,6 @@ void SystemInit (void)
196187

197188
/*!< Disable all interrupts */
198189
RCC->CIR = 0x00000000;
199-
200-
#ifdef DATA_IN_ExtSRAM
201-
SystemInit_ExtMemCtl();
202-
#endif /* DATA_IN_ExtSRAM */
203190

204191
/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
205192
SetSysClock();
@@ -346,17 +333,17 @@ static void SetSysClock(void)
346333
/* Power enable */
347334
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
348335

349-
/* Select the Voltage Range 2 (1.5 V) */
350-
PWR->CR = PWR_CR_VOS_1;
336+
/* Select the Voltage Range 1 (1.8 V) */
337+
PWR->CR = PWR_CR_VOS_0;
351338

352339

353340
/* Wait Until the Voltage Regulator is ready */
354341
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
355342
{
356343
}
357344

358-
/* HCLK = SYSCLK /2*/
359-
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV2;
345+
/* HCLK = SYSCLK /1*/
346+
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
360347
/* PCLK2 = HCLK /1*/
361348
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
362349

@@ -379,131 +366,6 @@ static void SetSysClock(void)
379366
}
380367
}
381368

382-
#ifdef DATA_IN_ExtSRAM
383-
/**
384-
* @brief Setup the external memory controller.
385-
* Called in SystemInit() function before jump to main.
386-
* This function configures the external SRAM mounted on STM32L152D_EVAL board
387-
* This SRAM will be used as program data memory (including heap and stack).
388-
* @param None
389-
* @retval None
390-
*/
391-
void SystemInit_ExtMemCtl(void)
392-
{
393-
/*-- GPIOs Configuration -----------------------------------------------------*/
394-
/*
395-
+-------------------+--------------------+------------------+------------------+
396-
+ SRAM pins assignment +
397-
+-------------------+--------------------+------------------+------------------+
398-
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
399-
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
400-
| PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
401-
| PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
402-
| PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
403-
| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
404-
| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
405-
| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
406-
| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
407-
| PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
408-
| PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+
409-
| PD15 <-> FSMC_D1 |--------------------+
410-
+-------------------+
411-
*/
412-
413-
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
414-
RCC->AHBENR = 0x000080D8;
415-
416-
/* Connect PDx pins to FSMC Alternate function */
417-
GPIOD->AFR[0] = 0x00CC00CC;
418-
GPIOD->AFR[1] = 0xCCCCCCCC;
419-
/* Configure PDx pins in Alternate function mode */
420-
GPIOD->MODER = 0xAAAA0A0A;
421-
/* Configure PDx pins speed to 40 MHz */
422-
GPIOD->OSPEEDR = 0xFFFF0F0F;
423-
/* Configure PDx pins Output type to push-pull */
424-
GPIOD->OTYPER = 0x00000000;
425-
/* No pull-up, pull-down for PDx pins */
426-
GPIOD->PUPDR = 0x00000000;
427-
428-
/* Connect PEx pins to FSMC Alternate function */
429-
GPIOE->AFR[0] = 0xC00000CC;
430-
GPIOE->AFR[1] = 0xCCCCCCCC;
431-
/* Configure PEx pins in Alternate function mode */
432-
GPIOE->MODER = 0xAAAA800A;
433-
/* Configure PEx pins speed to 40 MHz */
434-
GPIOE->OSPEEDR = 0xFFFFC00F;
435-
/* Configure PEx pins Output type to push-pull */
436-
GPIOE->OTYPER = 0x00000000;
437-
/* No pull-up, pull-down for PEx pins */
438-
GPIOE->PUPDR = 0x00000000;
439-
440-
/* Connect PFx pins to FSMC Alternate function */
441-
GPIOF->AFR[0] = 0x00CCCCCC;
442-
GPIOF->AFR[1] = 0xCCCC0000;
443-
/* Configure PFx pins in Alternate function mode */
444-
GPIOF->MODER = 0xAA000AAA;
445-
/* Configure PFx pins speed to 40 MHz */
446-
GPIOF->OSPEEDR = 0xFF000FFF;
447-
/* Configure PFx pins Output type to push-pull */
448-
GPIOF->OTYPER = 0x00000000;
449-
/* No pull-up, pull-down for PFx pins */
450-
GPIOF->PUPDR = 0x00000000;
451-
452-
/* Connect PGx pins to FSMC Alternate function */
453-
GPIOG->AFR[0] = 0x00CCCCCC;
454-
GPIOG->AFR[1] = 0x00000C00;
455-
/* Configure PGx pins in Alternate function mode */
456-
GPIOG->MODER = 0x00200AAA;
457-
/* Configure PGx pins speed to 40 MHz */
458-
GPIOG->OSPEEDR = 0x00300FFF;
459-
/* Configure PGx pins Output type to push-pull */
460-
GPIOG->OTYPER = 0x00000000;
461-
/* No pull-up, pull-down for PGx pins */
462-
GPIOG->PUPDR = 0x00000000;
463-
464-
/*-- FSMC Configuration ------------------------------------------------------*/
465-
/* Enable the FSMC interface clock */
466-
RCC->AHBENR = 0x400080D8;
467-
468-
/* Configure and enable Bank1_SRAM3 */
469-
FSMC_Bank1->BTCR[4] = 0x00001011;
470-
FSMC_Bank1->BTCR[5] = 0x00000300;
471-
FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
472-
/*
473-
Bank1_SRAM3 is configured as follow:
474-
475-
p.FSMC_AddressSetupTime = 0;
476-
p.FSMC_AddressHoldTime = 0;
477-
p.FSMC_DataSetupTime = 3;
478-
p.FSMC_BusTurnAroundDuration = 0;
479-
p.FSMC_CLKDivision = 0;
480-
p.FSMC_DataLatency = 0;
481-
p.FSMC_AccessMode = FSMC_AccessMode_A;
482-
483-
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
484-
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
485-
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
486-
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
487-
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
488-
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
489-
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
490-
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
491-
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
492-
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
493-
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
494-
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
495-
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
496-
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
497-
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
498-
499-
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
500-
501-
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
502-
*/
503-
504-
}
505-
#endif /* DATA_IN_ExtSRAM */
506-
507369
/**
508370
* @}
509371
*/

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PinNames.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ extern "C" {
3939
// MODE (see GPIOMode_TypeDef structure)
4040
// OTYPE (see GPIOOType_TypeDef structure)
4141
// PUPD (see GPIOPuPd_TypeDef structure)
42-
// AFNUM (see AF_mapping constant table)
42+
// AFNUM (see AF_mapping constant table, 0xFF is not used)
4343
#define STM_PIN_DATA(MODE, OTYPE, PUPD, AFNUM) (((AFNUM)<<8)|((PUPD)<<4)|((OTYPE)<<2)|((MODE)<<0))
4444
#define STM_PIN_MODE(X) (((X)>>0) & 0x3)
4545
#define STM_PIN_OTYPE(X) (((X)>>2) & 0x1)

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/device.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@
3939
#define DEVICE_ANALOGIN 0
4040
#define DEVICE_ANALOGOUT 0
4141

42-
#define DEVICE_SERIAL 0
42+
#define DEVICE_SERIAL 1
4343

4444
#define DEVICE_I2C 0
4545
#define DEVICE_I2CSLAVE 0
@@ -61,7 +61,7 @@
6161

6262
#define DEVICE_DEBUG_AWARENESS 0
6363

64-
#define DEVICE_STDIO_MESSAGES 0
64+
#define DEVICE_STDIO_MESSAGES 1
6565

6666
//#define DEVICE_ERROR_RED 0
6767

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_api.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@
3434
uint32_t gpio_set(PinName pin) {
3535
if (pin == NC) return 0;
3636

37-
pin_function(pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0));
37+
pin_function(pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
3838

3939
return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
4040
}
@@ -78,10 +78,10 @@ void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
7878

7979
// Configure GPIO
8080
if (direction == PIN_OUTPUT) {
81-
pin_function(pin, STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0));
81+
pin_function(pin, STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF));
8282
}
8383
else { // PIN_INPUT
84-
pin_function(pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0));
84+
pin_function(pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
8585
}
8686
}
8787

@@ -91,9 +91,9 @@ void gpio_mode(gpio_t *obj, PinMode mode) {
9191

9292
void gpio_dir(gpio_t *obj, PinDirection direction) {
9393
if (direction == PIN_OUTPUT) {
94-
pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0));
94+
pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF));
9595
}
9696
else { // PIN_INPUT
97-
pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0));
97+
pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
9898
}
9999
}

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/pinmap.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -85,8 +85,8 @@ void pin_function(PinName pin, int data) {
8585
GPIO_Init(gpio, &GPIO_InitStructure);
8686

8787
// Configure Alternate Function
88-
if (afnum > 0) {
89-
GPIO_PinAFConfig(gpio, (uint16_t)(1 << pin_index), afnum);
88+
if (afnum != 0xFF) {
89+
GPIO_PinAFConfig(gpio, (uint16_t)pin_index, afnum);
9090
}
9191

9292
// *** TODO ***

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/port_api.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -88,10 +88,10 @@ void port_dir(port_t *obj, PinDirection dir) {
8888
for (i = 0; i < 16; i++) { // Process all pins
8989
if (obj->mask & (1 << i)) { // If the pin is used
9090
if (dir == PIN_OUTPUT) {
91-
pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0));
91+
pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF));
9292
}
9393
else { // PIN_INPUT
94-
pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0));
94+
pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
9595
}
9696
}
9797
}

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/serial_api.c

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -34,14 +34,14 @@
3434
#include <string.h>
3535

3636
static const PinMap PinMap_UART_TX[] = {
37-
{PA_9, UART_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)},
38-
{PA_2, UART_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)},
37+
{PA_9, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_USART1)},
38+
{PA_2, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_USART2)},
3939
{NC, NC, 0}
4040
};
4141

4242
static const PinMap PinMap_UART_RX[] = {
43-
{PA_10, UART_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)},
44-
{PA_3, UART_2, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)},
43+
{PA_10, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_USART1)},
44+
{PA_3, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_USART2)},
4545
{NC, NC, 0}
4646
};
4747

@@ -94,7 +94,9 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
9494
// Configure the UART pins
9595
pinmap_pinout(tx, PinMap_UART_TX);
9696
pinmap_pinout(rx, PinMap_UART_RX);
97-
97+
pin_mode(tx, PullUp);
98+
pin_mode(rx, PullUp);
99+
98100
// Configure UART
99101
obj->baudrate = 9600;
100102
obj->databits = USART_WordLength_8b;

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