Merge pull request #9888 from ARMmbed/feature-armc6

ARM Toolchain update to ARM Compiler 6.11(ARMC6)

Author: 0xc0170

TESTS/mbed_platform/stats_sys/main.cpp

@@ -39,7 +39,7 @@ void test_sys_info()
 
 #if defined(__IAR_SYSTEMS_ICC__)
     TEST_ASSERT_EQUAL(IAR, stats.compiler_id);
-#elif defined(__CC_ARM)
+#elif defined(__ARMCC_VERSION)
     TEST_ASSERT_EQUAL(ARM, stats.compiler_id);
 #elif defined(__GNUC__)
     TEST_ASSERT_EQUAL(GCC_ARM, stats.compiler_id);

features/storage/FEATURE_STORAGE/cfstore/configuration-store/configuration_store.h

@@ -163,7 +163,7 @@ typedef struct _ARM_CFSTORE_STATUS {
     ARM_CFSTORE_HANDLE (__name) = (ARM_CFSTORE_HANDLE) (__name##_buf_cFsToRe);  \
     memset((__name##_buf_cFsToRe), 0, CFSTORE_HANDLE_BUFSIZE)
 
-#if defined __MBED__ && (defined TOOLCHAIN_GCC_ARM || defined TOOLCHAIN_ARMC6)
+#if defined __MBED__ && (defined TOOLCHAIN_GCC_ARM || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)))
 /** @brief  Helper macro to swap 2 handles, which is useful for the Find() idiom. */
 #define CFSTORE_HANDLE_SWAP(__a_HaNdLe, __b_HaNdLe)         \
     do{ ARM_CFSTORE_HANDLE __temp_HaNdLe = (__a_HaNdLe);    \
@@ -174,6 +174,7 @@ typedef struct _ARM_CFSTORE_STATUS {
         __asm volatile("" ::: "memory");                    \
     }while(0)
 
+        
 #elif defined __MBED__ && defined TOOLCHAIN_ARM
 /** @brief  Helper macro to swap 2 handles, which is useful for the Find() idiom. */
 #define CFSTORE_HANDLE_SWAP(__a_HaNdLe, __b_HaNdLe)         \

platform/mbed_retarget.cpp

@@ -55,7 +55,11 @@ static SingletonPtr<PlatformMutex> _mutex;
 #   define PREFIX(x)    _sys##x
 #   define OPEN_MAX     _SYS_OPEN
 #   ifdef __MICROLIB
-#       pragma import(__use_full_stdio)
+#       if __ARMCC_VERSION >= 6010050
+asm(" .global __use_full_stdio\n");
+#       else
+#           pragma import(__use_full_stdio)
+#       endif
 #   endif
 
 #elif defined(__ICCARM__)
@@ -1253,7 +1257,7 @@ extern "C" WEAK caddr_t _sbrk(int incr)
     /* __HeapLimit is end of heap section */
     if (new_heap > (uint32_t) &__HeapLimit) {
         errno = ENOMEM;
-        return (caddr_t) -1;
+        return (caddr_t) - 1;
     }
 
     heap = new_heap;

rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h

@@ -104,26 +104,26 @@ __STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) {
 /// Get xPSR Register - emulate M profile: SP_usr - (8*4)
 /// \return      xPSR Register value
 #if defined(__CC_ARM)
+#pragma push
+#pragma arm
 static __asm    uint32_t __get_PSP (void) {
-  arm
   sub   sp, sp, #4
   stm   sp, {sp}^
   pop   {r0}
   sub   r0, r0, #32
   bx    lr
 }
+#pragma pop
 #else
 #ifdef __ICCARM__
 __arm
+#else
+__attribute__((target("arm")))
 #endif
 __STATIC_INLINE uint32_t __get_PSP (void) {
   register uint32_t ret;
 
   __ASM volatile (
-#ifndef __ICCARM__
-    ".syntax unified\n\t"
-    ".arm\n\t"
-#endif
     "sub  sp,sp,#4\n\t"
     "stm  sp,{sp}^\n\t"
     "pop  {%[ret]}\n\t"

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct

@@ -53,11 +53,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE  {
 LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
   ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
    *(InRoot$$Sections)
-   .ANY (+RO)
+   *(+RO)
   }
   ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
   RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE)  {  ; RW data
-   .ANY (+RW +ZI)
+   *(+RW +ZI)
   }
   ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
   }

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct

@@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE  {
 LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
   ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
    *(InRoot$$Sections)
-   .ANY (+RO)
+   *(+RO)
   }
   ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
   RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
-   .ANY (+RW +ZI)
+   *(+RW +ZI)
   }
   ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
   }

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct

@@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE  {
 LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
   ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
    *(InRoot$$Sections)
-   .ANY (+RO)
+   *(+RO)
   }
   ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
   RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
-   .ANY (+RW +ZI)
+   *(+RW +ZI)
   }
   ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
   }

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct

@@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE  {
 LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
   ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
    *(InRoot$$Sections)
-   .ANY (+RO)
+   *(+RO)
   }
   ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
   RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
-   .ANY (+RW +ZI)
+   *(+RW +ZI)
   }
   ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
   }

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct

@@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE  {
 LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
   ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
    *(InRoot$$Sections)
-   .ANY (+RO)
+   *(+RO)
   }
   ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
   RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
-   .ANY (+RW +ZI)
+   *(+RW +ZI)
   }
   ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
   }

targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_COMMON/softdevice/common/nrf_sdh_ble.c

@@ -65,7 +65,7 @@ NRF_SECTION_SET_DEF(sdh_ble_observers, nrf_sdh_ble_evt_observer_t, NRF_SDH_BLE_O
 
 
 //lint -save -e10 -e19 -e40 -e27 Illegal character (0x24)
-#if defined(__CC_ARM)
+#if defined(__ARMCC_VERSION)
     extern uint32_t  Image$$RW_IRAM1$$Base;
     uint32_t const * const m_ram_start = &Image$$RW_IRAM1$$Base;
 #elif defined(__ICCARM__)