RISC-V Simulator

A C++ and Python implementation of RISC-V Simulation.
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CS204 Project:RISC-V Assembler

The aim of this project is to simulate the machine level execution of RISC-V as well as the execution of RISC-V 32-bit instructions using a high level language. The Project also aims to give final updates to the user regarding each step of the execution of the program. It also returns the final status of the memory and registers as output for the user to analyse the working of their programs thoroughly. The Project currently allows the user to use 26 different instructions and can be extended to allow the use of any number of instructions as long as the instructions are supported by 32-bit RISC-V ISA. The program executes each instruction using five stages as described in the RISC-V architecture. The instruction memory size is upto 1000 instructions.

Table of Contents

• Getting Started: Installation and Running
• Screenshots
• Contributors

Getting Started: Installation and running

Prerequisites

• pip (>21.0.3)
• python (>3.7)

Libraries Used

Back-end - Python3 and G++

• os: for getting and adding path to certain file locations.
• sys: for reading and editing files with ease.

Front-end - Python3

• PyQT5: for the Graphic User Interface.
• qdarkstyle: for dark theme

Running the GUI version

• Your computer should have Python3, G++ and Makefile installed.You can check if they are installed or not by using the following commands

    python3 --version
    g++ --version 
    make --version
 

• Download the zip file of the repository
• cd into the CS_204_RISCV then to src

   cd CS_204_RISCV/src
 

• Now run the following command in terminal

    make
  

• The above commands will open the GUI. You have to press ASSEMBLE, which will compile and run the cpp files.
• Wait for the message "Ready to run" and then press the RUN button.
• This will print the output log, update the register values and data memory in the GUI.

Running the Basic version without GUI

• Type the following command after cd into the src folder

    g++ main.cpp myRISCVSim.cpp -I ../include
  

• This will run the program and output the output log in output_log.mem, data memory in D_memory.mem and register values in register.mem

Feeding Input to the program

• The src Folder contains a test_case.mem file in which the machine code you want to run will go in the following format (containing the instruction code as well as the pc).The exit code will be 0xEF000011

    0x0 0x00500513
    0x4 0x008000EF
    0x8 0x0440006F
  

• The machine code in this format for the 3 test cases i.e. bubblesort (bubblesort.mem), sum of array element (arraysum.mem) and fibonacci (fibonacci.mem) are provided in the root directory. You can copy-paste the code from there to test_case.mem file in src folder for running them.
• If you want to run any code written in assembly, Go to venus simulator (online), copy-paste the dump in the input.py file in src folder, then run the inp.py file. It will convert the dump into the required assembly format and write it in the test_case.mem file. You can run the code to see the output.

Output Format

Check the generated folder for details of compilation. It contains:

• output_log.mem : contains general stats about the different stages like fetch,decode,ALU,memory access,register writeback and details of changes in temporary registers for each cycle
• data_out.mem: details of instruction memory
• register.mem: details of registers
• D_Memory.mem: details of data memory

ScreenShots

Linux View

Windows View

Contributors

Anushtha Prakash   Arpit Kumar Gautam   Aryaman Gupta   Ashima Goyal