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1. My-Portfolio My-Portfolio Public

   Get to know me!!

   HTML

2. AHB-Lite-DMA-controller-for-memory-to-memory-transfer-using-SRAM-slaves AHB-Lite-DMA-controller-for-memory-to-memory-transfer-using-SRAM-slaves Public

   Synthesizable AHB-Lite DMA controller that performs memory-to-memory transfers between two SRAM blocks, supporting single and burst transfers, interrupt-driven completion, and performance monitoring

   SystemVerilog 1

3. Hardware-Accelerator-for-Scaled-Dot-Product-Attention-in-Transformer-Architectures Hardware-Accelerator-for-Scaled-Dot-Product-Attention-in-Transformer-Architectures Public

   Verilog 1

4. Wishbone-to-I2C-bus-controller-IP-Verification Wishbone-to-I2C-bus-controller-IP-Verification Public

   Forked from zli87/Wishbone-to-I2C-bus-controller-IP-Verification

   ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.

   VHDL

5. APB-AMBA-Protocol-Implementation-in-RTL APB-AMBA-Protocol-Implementation-in-RTL Public

   Complete APB (Advanced Peripheral Bus) RTL implementation in Verilog following ARM AMBA specification. Includes master, slave, decoder modules with comprehensive testbench.

   Verilog 1

6. Floating-Point-MAC-Matrix-Multiplier Floating-Point-MAC-Matrix-Multiplier Public

   Verilog implementation of a floating-point multiply-accumulate (MAC) engine for matrix multiplication using DesignWare IP, with SRAM-based memory interface, handshake control, and timing analysis s…

   Verilog