apb_master.v

// APB Master Module
// Implements APB master interface per AMBA APB specification

module apb_master #(
    parameter ADDR_WIDTH = 32,
    parameter DATA_WIDTH = 32
)(
    input wire PCLK,
    input wire PRESETn,
    
    // Internal interface (from processor/controller)
    input wire req,                    // Transfer request
    input wire [ADDR_WIDTH-1:0] addr, // Address
    input wire write,                  // 1=write, 0=read
    input wire [DATA_WIDTH-1:0] wdata, // Write data
    output reg [DATA_WIDTH-1:0] rdata, // Read data
    output reg ready,                  // Transfer complete
    output reg error,                  // Transfer error
    
    // APB interface
    output reg PSEL,
    output reg PENABLE,
    output reg [ADDR_WIDTH-1:0] PADDR,
    output reg PWRITE,
    output reg [DATA_WIDTH-1:0] PWDATA,
    input wire [DATA_WIDTH-1:0] PRDATA,
    input wire PREADY,
    input wire PSLVERR
);

    // APB State Machine
    localparam IDLE = 2'b00;
    localparam SETUP = 2'b01;
    localparam ACCESS = 2'b10;
    
    reg [1:0] state;
    reg [1:0] next_state;
    
    // State machine
    always @(posedge PCLK or negedge PRESETn) begin
        if (!PRESETn) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end
    
    // Next state logic
    always @(*) begin
        case (state)
            IDLE: begin
                if (req)
                    next_state = SETUP;
                else
                    next_state = IDLE;
            end
            SETUP: begin
                next_state = ACCESS;
            end
            ACCESS: begin
                if (PREADY) begin
                    if (req)
                        next_state = SETUP;
                    else
                        next_state = IDLE;
                end else begin
                    next_state = ACCESS;
                end
            end
            default: next_state = IDLE;
        endcase
    end
    
    // APB signal generation
    always @(posedge PCLK or negedge PRESETn) begin
        if (!PRESETn) begin
            PSEL <= 1'b0;
            PENABLE <= 1'b0;
            PADDR <= 0;
            PWRITE <= 1'b0;
            PWDATA <= 0;
            ready <= 1'b0;
            error <= 1'b0;
            rdata <= 0;
        end else begin
            case (state)
                IDLE: begin
                    PSEL <= 1'b0;
                    PENABLE <= 1'b0;
                    ready <= 1'b0;
                    error <= 1'b0;
                    if (req) begin
                        PADDR <= addr;
                        PWRITE <= write;
                        if (write)
                            PWDATA <= wdata;
                    end
                end
                SETUP: begin
                    PSEL <= 1'b1;
                    PENABLE <= 1'b0;
                    PADDR <= addr;
                    PWRITE <= write;
                    if (write)
                        PWDATA <= wdata;
                end
                ACCESS: begin
                    PSEL <= 1'b1;
                    PENABLE <= 1'b1;
                    if (PREADY) begin
                        if (!PWRITE)
                            rdata <= PRDATA;
                        ready <= 1'b1;
                        error <= PSLVERR;
                        if (!req) begin
                            PSEL <= 1'b0;
                            PENABLE <= 1'b0;
                        end
                    end else begin
                        ready <= 1'b0;
                    end
                end
            endcase
        end
    end

endmodule