apb_top.v

// APB Top Module
// Connects APB Master, Decoder, and Slaves

module apb_top #(
    parameter ADDR_WIDTH = 32,
    parameter DATA_WIDTH = 32,
    parameter NUM_SLAVES = 4
)(
    input wire PCLK,
    input wire PRESETn,
    
    // Master interface
    input wire req,
    input wire [ADDR_WIDTH-1:0] addr,
    input wire write,
    input wire [DATA_WIDTH-1:0] wdata,
    output wire [DATA_WIDTH-1:0] rdata,
    output wire ready,
    output wire error,
    
    // Slave register interfaces (for monitoring)
    output wire [DATA_WIDTH-1:0] slave0_reg [0:15],
    output wire [DATA_WIDTH-1:0] slave1_reg [0:15],
    output wire [DATA_WIDTH-1:0] slave2_reg [0:15],
    output wire [DATA_WIDTH-1:0] slave3_reg [0:15]
);

    // Master signals
    wire master_PSEL;
    wire master_PENABLE;
    wire [ADDR_WIDTH-1:0] master_PADDR;
    wire master_PWRITE;
    wire [DATA_WIDTH-1:0] master_PWDATA;
    wire [DATA_WIDTH-1:0] master_PRDATA;
    wire master_PREADY;
    wire master_PSLVERR;
    
    // Decoder signals
    wire [NUM_SLAVES-1:0] slave_sel;
    
    // Slave signals
    wire [NUM_SLAVES-1:0] slave_PSEL;
    wire [DATA_WIDTH-1:0] slave_PRDATA [0:NUM_SLAVES-1];
    wire [NUM_SLAVES-1:0] slave_PREADY;
    wire [NUM_SLAVES-1:0] slave_PSLVERR;
    
    // Internal register interfaces
    wire [DATA_WIDTH-1:0] slave_reg_data [0:NUM_SLAVES-1] [0:15];
    wire [NUM_SLAVES-1:0] slave_reg_write_en;
    wire [3:0] slave_reg_addr [0:NUM_SLAVES-1];
    
    // Assign slave PSEL from decoder
    assign slave_PSEL = slave_sel;
    
    // Multiplex slave responses (only one slave should respond at a time)
    assign master_PRDATA = (slave_sel[0] ? slave_PRDATA[0] : 0) |
                           (slave_sel[1] ? slave_PRDATA[1] : 0) |
                           (slave_sel[2] ? slave_PRDATA[2] : 0) |
                           (slave_sel[3] ? slave_PRDATA[3] : 0);
    assign master_PREADY = slave_PREADY[0] | slave_PREADY[1] | slave_PREADY[2] | slave_PREADY[3];
    assign master_PSLVERR = slave_PSLVERR[0] | slave_PSLVERR[1] | slave_PSLVERR[2] | slave_PSLVERR[3];
    
    // Assign slave register outputs
    genvar j;
    generate
        for (j = 0; j < 16; j = j + 1) begin : gen_regs
            assign slave0_reg[j] = slave_reg_data[0][j];
            assign slave1_reg[j] = slave_reg_data[1][j];
            assign slave2_reg[j] = slave_reg_data[2][j];
            assign slave3_reg[j] = slave_reg_data[3][j];
        end
    endgenerate
    
    // Instantiate APB Master
    apb_master #(
        .ADDR_WIDTH(ADDR_WIDTH),
        .DATA_WIDTH(DATA_WIDTH)
    ) u_master (
        .PCLK(PCLK),
        .PRESETn(PRESETn),
        .req(req),
        .addr(addr),
        .write(write),
        .wdata(wdata),
        .rdata(rdata),
        .ready(ready),
        .error(error),
        .PSEL(master_PSEL),
        .PENABLE(master_PENABLE),
        .PADDR(master_PADDR),
        .PWRITE(master_PWRITE),
        .PWDATA(master_PWDATA),
        .PRDATA(master_PRDATA),
        .PREADY(master_PREADY),
        .PSLVERR(master_PSLVERR)
    );
    
    // Instantiate APB Decoder
    apb_decoder #(
        .ADDR_WIDTH(ADDR_WIDTH),
        .NUM_SLAVES(NUM_SLAVES)
    ) u_decoder (
        .PADDR(master_PADDR),
        .PSEL(master_PSEL),
        .slave_sel(slave_sel)
    );
    
    // Instantiate APB Slaves
    genvar k;
    generate
        for (k = 0; k < NUM_SLAVES; k = k + 1) begin : gen_slaves
            apb_slave #(
                .ADDR_WIDTH(ADDR_WIDTH),
                .DATA_WIDTH(DATA_WIDTH),
                .BASE_ADDR(k * 32'h1000),
                .ADDR_MASK(32'hFFFF_F000)
            ) u_slave (
                .PCLK(PCLK),
                .PRESETn(PRESETn),
                .PSEL(slave_PSEL[k]),
                .PENABLE(master_PENABLE),
                .PADDR(master_PADDR),
                .PWRITE(master_PWRITE),
                .PWDATA(master_PWDATA),
                .PRDATA(slave_PRDATA[k]),
                .PREADY(slave_PREADY[k]),
                .PSLVERR(slave_PSLVERR[k]),
                .reg_data(slave_reg_data[k]),
                .reg_write_en(slave_reg_write_en[k]),
                .reg_addr(slave_reg_addr[k])
            );
        end
    endgenerate

endmodule