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Author: AarfaSheikh

APB_README.md

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+// APB Decoder Module
+// Decodes address and generates PSEL for each slave
+
+module apb_decoder #(
+    parameter ADDR_WIDTH = 32,
+    parameter NUM_SLAVES = 4
+)(
+    input wire [ADDR_WIDTH-1:0] PADDR,
+    input wire PSEL,  // Master PSEL
+    output reg [NUM_SLAVES-1:0] slave_sel  // One-hot slave select
+);
+
+    // Address ranges for each slave (can be parameterized)
+    // Slave 0: 0x0000_0000 - 0x0000_0FFF
+    // Slave 1: 0x0000_1000 - 0x0000_1FFF
+    // Slave 2: 0x0000_2000 - 0x0000_2FFF
+    // Slave 3: 0x0000_3000 - 0x0000_3FFF
+    
+    always @(*) begin
+        slave_sel = 0;
+        if (PSEL) begin
+            case (PADDR[15:12])
+                4'h0: slave_sel[0] = 1'b1;
+                4'h1: slave_sel[1] = 1'b1;
+                4'h2: slave_sel[2] = 1'b1;
+                4'h3: slave_sel[3] = 1'b1;
+                default: slave_sel = 0; // No slave selected
+            endcase
+        end
+    end
+
+endmodule
+

apb_decoder.v

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+// APB Master Module
+// Implements APB master interface per AMBA APB specification
+
+module apb_master #(
+    parameter ADDR_WIDTH = 32,
+    parameter DATA_WIDTH = 32
+)(
+    input wire PCLK,
+    input wire PRESETn,
+    
+    // Internal interface (from processor/controller)
+    input wire req,                    // Transfer request
+    input wire [ADDR_WIDTH-1:0] addr, // Address
+    input wire write,                  // 1=write, 0=read
+    input wire [DATA_WIDTH-1:0] wdata, // Write data
+    output reg [DATA_WIDTH-1:0] rdata, // Read data
+    output reg ready,                  // Transfer complete
+    output reg error,                  // Transfer error
+    
+    // APB interface
+    output reg PSEL,
+    output reg PENABLE,
+    output reg [ADDR_WIDTH-1:0] PADDR,
+    output reg PWRITE,
+    output reg [DATA_WIDTH-1:0] PWDATA,
+    input wire [DATA_WIDTH-1:0] PRDATA,
+    input wire PREADY,
+    input wire PSLVERR
+);
+
+    // APB State Machine
+    localparam IDLE = 2'b00;
+    localparam SETUP = 2'b01;
+    localparam ACCESS = 2'b10;
+    
+    reg [1:0] state;
+    reg [1:0] next_state;
+    
+    // State machine
+    always @(posedge PCLK or negedge PRESETn) begin
+        if (!PRESETn) begin
+            state <= IDLE;
+        end else begin
+            state <= next_state;
+        end
+    end
+    
+    // Next state logic
+    always @(*) begin
+        case (state)
+            IDLE: begin
+                if (req)
+                    next_state = SETUP;
+                else
+                    next_state = IDLE;
+            end
+            SETUP: begin
+                next_state = ACCESS;
+            end
+            ACCESS: begin
+                if (PREADY) begin
+                    if (req)
+                        next_state = SETUP;
+                    else
+                        next_state = IDLE;
+                end else begin
+                    next_state = ACCESS;
+                end
+            end
+            default: next_state = IDLE;
+        endcase
+    end
+    
+    // APB signal generation
+    always @(posedge PCLK or negedge PRESETn) begin
+        if (!PRESETn) begin
+            PSEL <= 1'b0;
+            PENABLE <= 1'b0;
+            PADDR <= 0;
+            PWRITE <= 1'b0;
+            PWDATA <= 0;
+            ready <= 1'b0;
+            error <= 1'b0;
+            rdata <= 0;
+        end else begin
+            case (state)
+                IDLE: begin
+                    PSEL <= 1'b0;
+                    PENABLE <= 1'b0;
+                    ready <= 1'b0;
+                    error <= 1'b0;
+                    if (req) begin
+                        PADDR <= addr;
+                        PWRITE <= write;
+                        if (write)
+                            PWDATA <= wdata;
+                    end
+                end
+                SETUP: begin
+                    PSEL <= 1'b1;
+                    PENABLE <= 1'b0;
+                    PADDR <= addr;
+                    PWRITE <= write;
+                    if (write)
+                        PWDATA <= wdata;
+                end
+                ACCESS: begin
+                    PSEL <= 1'b1;
+                    PENABLE <= 1'b1;
+                    if (PREADY) begin
+                        if (!PWRITE)
+                            rdata <= PRDATA;
+                        ready <= 1'b1;
+                        error <= PSLVERR;
+                        if (!req) begin
+                            PSEL <= 1'b0;
+                            PENABLE <= 1'b0;
+                        end
+                    end else begin
+                        ready <= 1'b0;
+                    end
+                end
+            endcase
+        end
+    end
+
+endmodule
+

apb_master.v

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+// APB Slave Module
+// Implements APB slave interface per AMBA APB specification
+
+module apb_slave #(
+    parameter ADDR_WIDTH = 32,
+    parameter DATA_WIDTH = 32,
+    parameter BASE_ADDR = 32'h0000_0000,
+    parameter ADDR_MASK = 32'hFFFF_0000  // Address mask for decoding
+)(
+    input wire PCLK,
+    input wire PRESETn,
+    
+    // APB interface
+    input wire PSEL,
+    input wire PENABLE,
+    input wire [ADDR_WIDTH-1:0] PADDR,
+    input wire PWRITE,
+    input wire [DATA_WIDTH-1:0] PWDATA,
+    output reg [DATA_WIDTH-1:0] PRDATA,
+    output reg PREADY,
+    output reg PSLVERR,
+    
+    // Internal register interface
+    output reg [DATA_WIDTH-1:0] reg_data [0:15], // 16 registers
+    output reg reg_write_en,
+    output reg [3:0] reg_addr
+);
+
+    // Address decoding
+    wire slave_sel;
+    assign slave_sel = ((PADDR & ADDR_MASK) == (BASE_ADDR & ADDR_MASK)) && PSEL;
+    
+    // Internal address (offset from base address)
+    wire [3:0] internal_addr;
+    assign internal_addr = PADDR[5:2]; // 4-bit address for 16 registers (word-aligned)
+    
+    // PREADY generation (can be modified for wait states)
+    always @(posedge PCLK or negedge PRESETn) begin
+        if (!PRESETn) begin
+            PREADY <= 1'b0;
+        end else begin
+            if (slave_sel && PENABLE) begin
+                PREADY <= 1'b1; // Ready in access phase (can add wait states)
+            end else if (slave_sel && !PENABLE) begin
+                PREADY <= 1'b0; // Setup phase
+            end else begin
+                PREADY <= 1'b0;
+            end
+        end
+    end
+    
+    // Write operation
+    always @(posedge PCLK or negedge PRESETn) begin
+        if (!PRESETn) begin
+            reg_write_en <= 1'b0;
+            reg_addr <= 0;
+            for (integer i = 0; i < 16; i = i + 1) begin
+                reg_data[i] <= 0;
+            end
+        end else begin
+            reg_write_en <= 1'b0;
+            if (slave_sel && PENABLE && PWRITE) begin
+                reg_data[internal_addr] <= PWDATA;
+                reg_write_en <= 1'b1;
+                reg_addr <= internal_addr;
+            end
+        end
+    end
+    
+    // Read operation
+    always @(posedge PCLK or negedge PRESETn) begin
+        if (!PRESETn) begin
+            PRDATA <= 0;
+        end else begin
+            if (slave_sel && !PWRITE) begin
+                PRDATA <= reg_data[internal_addr];
+            end else begin
+                PRDATA <= 0;
+            end
+        end
+    end
+    
+    // Error generation (optional - can be customized)
+    always @(posedge PCLK or negedge PRESETn) begin
+        if (!PRESETn) begin
+            PSLVERR <= 1'b0;
+        end else begin
+            if (slave_sel && PENABLE) begin
+                // Example: Error if accessing reserved register (addr > 15)
+                if (internal_addr > 15) begin
+                    PSLVERR <= 1'b1;
+                end else begin
+                    PSLVERR <= 1'b0;
+                end
+            end else begin
+                PSLVERR <= 1'b0;
+            end
+        end
+    end
+
+endmodule
+