Pinned Loading

1. RISC-V-RV32I RISC-V-RV32I Public

   5-stage pipelined RISC-V processor with extended custom instructions to accelerate matrix operations.

   SystemVerilog

2. tt10-Space-Invaders-Game tt10-Space-Invaders-Game Public

   Verilog

3. tinyqv-affinex tinyqv-affinex Public

   Memory mapped custom peripheral for affine transformations.

   Python

4. picoMIPS picoMIPS Public

   SystemVerilog

5. Cache-Controller Cache-Controller Public

   Direct-mapped write-through cache and controller for a single-cycle processor system.

   Verilog

6. Croc_SoC Croc_SoC Public

   Forked from pulp-platform/croc

   A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

   SystemVerilog