test(tx): update all tests to use AdatFamily enum

Author: AkiyukiOkayasu

src/adat_tx.veryl

@@ -132,7 +132,7 @@ module tb_adat_tx_48k;
 
   adat_rx_adat_tx #(
       .CLK_FREQ(CLK_FREQ),
-      .SAMPLE_RATE(SAMPLE_RATE)
+      .ADAT_FAMILY(1'b1)
   ) u_dut (
       .i_clk(clk),
       .i_rst(rst),
@@ -365,7 +365,6 @@ embed (inline) sv{{{
 
 module tb_echo_loopback_88k;
   localparam int CLK_FREQ = 50_000_000;
-  localparam int SAMPLE_RATE = 88200;
   localparam int CHECK_FRAMES = 11;
 
   logic clk;
@@ -403,7 +402,7 @@ module tb_echo_loopback_88k;
 
   adat_rx_adat_tx #(
       .CLK_FREQ(CLK_FREQ),
-      .SAMPLE_RATE(SAMPLE_RATE)
+      .ADAT_FAMILY(1'b0)
   ) u_tx (
       .i_clk(clk),
       .i_rst(rst),
@@ -635,7 +634,6 @@ embed (inline) sv{{{
 
 module tb_echo_loopback_96k;
   localparam int CLK_FREQ = 50_000_000;
-  localparam int SAMPLE_RATE = 96000;
   localparam int CHECK_FRAMES = 11;
 
   logic clk;
@@ -673,7 +671,7 @@ module tb_echo_loopback_96k;
 
   adat_rx_adat_tx #(
       .CLK_FREQ(CLK_FREQ),
-      .SAMPLE_RATE(SAMPLE_RATE)
+      .ADAT_FAMILY(1'b1)
   ) u_tx (
       .i_clk(clk),
       .i_rst(rst),
@@ -905,7 +903,7 @@ embed (inline) sv{{{
 
 module adat_tx #(
     parameter int CLK_FREQ = 50_000_000,
-    parameter int SAMPLE_RATE = 48000
+    parameter logic ADAT_FAMILY = 1'b1
 ) (
     input logic i_clk,
     input logic i_rst,
@@ -918,7 +916,7 @@ module adat_tx #(
 
   adat_rx_adat_tx #(
       .CLK_FREQ(CLK_FREQ),
-      .SAMPLE_RATE(SAMPLE_RATE)
+      .ADAT_FAMILY(ADAT_FAMILY)
   ) u_impl (
       .i_clk(i_clk),
       .i_rst(i_rst),
@@ -955,7 +953,6 @@ endmodule
 
 module tb_echo_loopback;
   localparam int CLK_FREQ = 50_000_000;
-  localparam int SAMPLE_RATE = 48000;
   localparam int CHECK_FRAMES = 11;
 
   logic clk;
@@ -995,7 +992,7 @@ module tb_echo_loopback;
 
   adat_tx #(
       .CLK_FREQ(CLK_FREQ),
-      .SAMPLE_RATE(SAMPLE_RATE)
+      .ADAT_FAMILY(1'b1)
   ) u_tx (
       .i_clk(clk),
       .i_rst(rst),

src/tx_bit_serializer.veryl

@@ -143,7 +143,7 @@ module tb_tx_bit_serializer;
   logic rst;
   logic [255:0] frame_data;
   logic load;
-  logic [31:0] sample_rate;
+  logic family;
   logic bit_out;
   logic bit_valid;
   logic frame_done;
@@ -160,7 +160,7 @@ module tb_tx_bit_serializer;
       .i_rst(rst),
       .i_frame_data(frame_data),
       .i_load(load),
-      .i_sample_rate(sample_rate),
+      .i_family(family),
       .o_bit(bit_out),
       .o_bit_valid(bit_valid),
       .o_frame_done(frame_done)
@@ -182,14 +182,16 @@ module tb_tx_bit_serializer;
     end
   endfunction
 
-  task automatic run_frame(input [255:0] frame, input int sr, input string tag);
+  task automatic run_frame(input [255:0] frame, input logic fam, input string tag);
     int bit_idx;
     int cycles_since_prev;
     int timeout;
     int exp_cycles;
+    int sr;
     begin
+      sr = fam ? 48000 : 44100;
       frame_data = frame;
-      sample_rate = sr;
+      family = fam;
       load = 1'b1;
       @(posedge clk);
       load = 1'b0;
@@ -250,14 +252,14 @@ module tb_tx_bit_serializer;
     rst = 1'b0;
     frame_data = 256'd0;
     load = 1'b0;
-    sample_rate = 32'd48000;
+    family = 1'b1;
 
     repeat (2) @(posedge clk);
     rst = 1'b1;
     repeat (2) @(posedge clk);
 
-    run_frame({8'hD3, 240'h00, 8'h5A}, 48000, "frame0_48k");
-    run_frame(256'h0123456789ABCDEF00112233445566778899AABBCCDDEEFF13579BDF2468ACE0, 44100,
+    run_frame({8'hD3, 240'h00, 8'h5A}, 1'b1, "frame0_48k");
+    run_frame(256'h0123456789ABCDEF00112233445566778899AABBCCDDEEFF13579BDF2468ACE0, 1'b0,
               "frame1_44k1");
 
     if (pass) begin