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anshuma1ideak
anshuma1
authored and
ideak
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drm/i915/dg1: Adjust the AUDIO power domain
DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power well. Adjusting the power domain accordingly to POWER_DOMAIN_AUDIO_MMIO for audio detection and POWER_DOMAIN_AUDIO_PLAYBACK for audio playback. While doing this it requires to use POWER_DOMAIN_AUDIO_MMIO power domain instead of POWER_DOMAIN_AUDIO in crtc power domain mask and POWER_DOMAIN_AUDIO_PLAYBACK with intel_display_power_{get, put} to enable/disable display audio codec power. It will save the power in use cases when DP/HDMI connectors configured with PIPE_A without any audio playback. v1: Changes since RFC - changed power domain names. [Imre] - Removed TC{3,6}, AUX_USBC{3,6} and TBT from DG1 power well and PW_3 power domains. [Imre] - Fixed the order of powe wells , power domains and its registration. [Imre] v2: - Not allowe DC states when AUDIO_MMIO domain enabled. [Imre] v3: - Squashes the commits of series to avoid build failure. Cc: Ville Syrjälä <[email protected]> Cc: Kai Vehmanen <[email protected]> Cc: Uma Shankar <[email protected]> Cc: Imre Deak <[email protected]> Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Anshuman Gupta <[email protected]> [Fix typo in commit message and in AUDIO_PLAYBACK domain name] Signed-off-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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5 files changed

+223
-19
lines changed

5 files changed

+223
-19
lines changed

‎drivers/gpu/drm/i915/display/intel_audio.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1001,7 +1001,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
10011001
/* Catch potential impedance mismatches before they occur! */
10021002
BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
10031003

1004-
ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1004+
ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK);
10051005

10061006
if (dev_priv->audio_power_refcount++ == 0) {
10071007
if (DISPLAY_VER(dev_priv) >= 9) {
@@ -1034,7 +1034,7 @@ static void i915_audio_component_put_power(struct device *kdev,
10341034
if (IS_GEMINILAKE(dev_priv))
10351035
glk_force_audio_cdclk(dev_priv, false);
10361036

1037-
intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
1037+
intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK, cookie);
10381038
}
10391039

10401040
static void i915_audio_component_codec_wake_override(struct device *kdev,

‎drivers/gpu/drm/i915/display/intel_ddi.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3414,7 +3414,7 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
34143414
if (cpu_transcoder == TRANSCODER_EDP)
34153415
return false;
34163416

3417-
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3417+
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
34183418
return false;
34193419

34203420
return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &

‎drivers/gpu/drm/i915/display/intel_display.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3931,7 +3931,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
39313931
}
39323932

39333933
if (HAS_DDI(dev_priv) && crtc_state->has_audio)
3934-
mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
3934+
mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO);
39353935

39363936
if (crtc_state->shared_dpll)
39373937
mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);

‎drivers/gpu/drm/i915/display/intel_display_power.c

Lines changed: 217 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -107,8 +107,10 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
107107
return "PORT_OTHER";
108108
case POWER_DOMAIN_VGA:
109109
return "VGA";
110-
case POWER_DOMAIN_AUDIO:
111-
return "AUDIO";
110+
case POWER_DOMAIN_AUDIO_MMIO:
111+
return "AUDIO_MMIO";
112+
case POWER_DOMAIN_AUDIO_PLAYBACK:
113+
return "AUDIO_PLAYBACK";
112114
case POWER_DOMAIN_AUX_A:
113115
return "AUX_A";
114116
case POWER_DOMAIN_AUX_B:
@@ -2509,7 +2511,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
25092511
BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
25102512
BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
25112513
BIT_ULL(POWER_DOMAIN_VGA) | \
2512-
BIT_ULL(POWER_DOMAIN_AUDIO) | \
2514+
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
2515+
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
25132516
BIT_ULL(POWER_DOMAIN_AUX_B) | \
25142517
BIT_ULL(POWER_DOMAIN_AUX_C) | \
25152518
BIT_ULL(POWER_DOMAIN_GMBUS) | \
@@ -2559,7 +2562,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
25592562
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
25602563
BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
25612564
BIT_ULL(POWER_DOMAIN_VGA) | \
2562-
BIT_ULL(POWER_DOMAIN_AUDIO) | \
2565+
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
2566+
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
25632567
BIT_ULL(POWER_DOMAIN_AUX_B) | \
25642568
BIT_ULL(POWER_DOMAIN_AUX_C) | \
25652569
BIT_ULL(POWER_DOMAIN_AUX_D) | \
@@ -2592,7 +2596,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
25922596
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
25932597
BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
25942598
BIT_ULL(POWER_DOMAIN_VGA) | \
2595-
BIT_ULL(POWER_DOMAIN_AUDIO) | \
2599+
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
2600+
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
25962601
BIT_ULL(POWER_DOMAIN_INIT))
25972602

25982603
#define BDW_DISPLAY_POWER_DOMAINS ( \
@@ -2608,7 +2613,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
26082613
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
26092614
BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
26102615
BIT_ULL(POWER_DOMAIN_VGA) | \
2611-
BIT_ULL(POWER_DOMAIN_AUDIO) | \
2616+
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
2617+
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
26122618
BIT_ULL(POWER_DOMAIN_INIT))
26132619

26142620
#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
@@ -2626,7 +2632,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
26262632
BIT_ULL(POWER_DOMAIN_AUX_B) | \
26272633
BIT_ULL(POWER_DOMAIN_AUX_C) | \
26282634
BIT_ULL(POWER_DOMAIN_AUX_D) | \
2629-
BIT_ULL(POWER_DOMAIN_AUDIO) | \
2635+
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
2636+
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
26302637
BIT_ULL(POWER_DOMAIN_VGA) | \
26312638
BIT_ULL(POWER_DOMAIN_INIT))
26322639
#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
@@ -2661,7 +2668,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
26612668
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
26622669
BIT_ULL(POWER_DOMAIN_AUX_B) | \
26632670
BIT_ULL(POWER_DOMAIN_AUX_C) | \
2664-
BIT_ULL(POWER_DOMAIN_AUDIO) | \
2671+
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
2672+
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
26652673
BIT_ULL(POWER_DOMAIN_VGA) | \
26662674
BIT_ULL(POWER_DOMAIN_INIT))
26672675
#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
@@ -2694,7 +2702,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
26942702
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
26952703
BIT_ULL(POWER_DOMAIN_AUX_B) | \
26962704
BIT_ULL(POWER_DOMAIN_AUX_C) | \
2697-
BIT_ULL(POWER_DOMAIN_AUDIO) | \
2705+
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
2706+
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
26982707
BIT_ULL(POWER_DOMAIN_VGA) | \
26992708
BIT_ULL(POWER_DOMAIN_INIT))
27002709
#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \
@@ -2774,7 +2783,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
27742783
BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
27752784
BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
27762785
BIT_ULL(POWER_DOMAIN_VGA) | \
2777-
BIT_ULL(POWER_DOMAIN_AUDIO) | \
2786+
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
2787+
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
27782788
BIT_ULL(POWER_DOMAIN_INIT))
27792789
/*
27802790
* - transcoder WD
@@ -2866,7 +2876,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
28662876
BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
28672877
BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
28682878
BIT_ULL(POWER_DOMAIN_VGA) | \
2869-
BIT_ULL(POWER_DOMAIN_AUDIO) | \
2879+
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
2880+
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
28702881
BIT_ULL(POWER_DOMAIN_INIT))
28712882

28722883
#define TGL_PW_2_POWER_DOMAINS ( \
@@ -2936,7 +2947,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
29362947
RKL_PW_4_POWER_DOMAINS | \
29372948
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
29382949
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2939-
BIT_ULL(POWER_DOMAIN_AUDIO) | \
2950+
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
2951+
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
29402952
BIT_ULL(POWER_DOMAIN_VGA) | \
29412953
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
29422954
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
@@ -2973,6 +2985,35 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
29732985
BIT_ULL(POWER_DOMAIN_AUX_B) | \
29742986
BIT_ULL(POWER_DOMAIN_INIT))
29752987

2988+
/*
2989+
* DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
2990+
*/
2991+
#define DG1_PW_3_POWER_DOMAINS ( \
2992+
TGL_PW_4_POWER_DOMAINS | \
2993+
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
2994+
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
2995+
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2996+
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
2997+
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
2998+
BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
2999+
BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
3000+
BIT_ULL(POWER_DOMAIN_VGA) | \
3001+
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
3002+
BIT_ULL(POWER_DOMAIN_INIT))
3003+
3004+
#define DG1_PW_2_POWER_DOMAINS ( \
3005+
DG1_PW_3_POWER_DOMAINS | \
3006+
BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
3007+
BIT_ULL(POWER_DOMAIN_INIT))
3008+
3009+
#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
3010+
DG1_PW_3_POWER_DOMAINS | \
3011+
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
3012+
BIT_ULL(POWER_DOMAIN_MODESET) | \
3013+
BIT_ULL(POWER_DOMAIN_AUX_A) | \
3014+
BIT_ULL(POWER_DOMAIN_AUX_B) | \
3015+
BIT_ULL(POWER_DOMAIN_INIT))
3016+
29763017
/*
29773018
* XE_LPD Power Domains
29783019
*
@@ -3018,7 +3059,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
30183059
XELPD_PW_B_POWER_DOMAINS | \
30193060
XELPD_PW_C_POWER_DOMAINS | \
30203061
XELPD_PW_D_POWER_DOMAINS | \
3021-
BIT_ULL(POWER_DOMAIN_AUDIO) | \
3062+
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
30223063
BIT_ULL(POWER_DOMAIN_VGA) | \
30233064
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
30243065
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
@@ -3059,6 +3100,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
30593100

30603101
#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
30613102
XELPD_PW_2_POWER_DOMAINS | \
3103+
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
30623104
BIT_ULL(POWER_DOMAIN_MODESET) | \
30633105
BIT_ULL(POWER_DOMAIN_AUX_A) | \
30643106
BIT_ULL(POWER_DOMAIN_AUX_B) | \
@@ -4445,6 +4487,165 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
44454487
},
44464488
};
44474489

4490+
static const struct i915_power_well_desc dg1_power_wells[] = {
4491+
{
4492+
.name = "always-on",
4493+
.always_on = true,
4494+
.domains = POWER_DOMAIN_MASK,
4495+
.ops = &i9xx_always_on_power_well_ops,
4496+
.id = DISP_PW_ID_NONE,
4497+
},
4498+
{
4499+
.name = "power well 1",
4500+
/* Handled by the DMC firmware */
4501+
.always_on = true,
4502+
.domains = 0,
4503+
.ops = &hsw_power_well_ops,
4504+
.id = SKL_DISP_PW_1,
4505+
{
4506+
.hsw.regs = &hsw_power_well_regs,
4507+
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
4508+
.hsw.has_fuses = true,
4509+
},
4510+
},
4511+
{
4512+
.name = "DC off",
4513+
.domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
4514+
.ops = &gen9_dc_off_power_well_ops,
4515+
.id = SKL_DISP_DC_OFF,
4516+
},
4517+
{
4518+
.name = "power well 2",
4519+
.domains = DG1_PW_2_POWER_DOMAINS,
4520+
.ops = &hsw_power_well_ops,
4521+
.id = SKL_DISP_PW_2,
4522+
{
4523+
.hsw.regs = &hsw_power_well_regs,
4524+
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
4525+
.hsw.has_fuses = true,
4526+
},
4527+
},
4528+
{
4529+
.name = "power well 3",
4530+
.domains = DG1_PW_3_POWER_DOMAINS,
4531+
.ops = &hsw_power_well_ops,
4532+
.id = ICL_DISP_PW_3,
4533+
{
4534+
.hsw.regs = &hsw_power_well_regs,
4535+
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
4536+
.hsw.irq_pipe_mask = BIT(PIPE_B),
4537+
.hsw.has_vga = true,
4538+
.hsw.has_fuses = true,
4539+
},
4540+
},
4541+
{
4542+
.name = "DDI A IO",
4543+
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
4544+
.ops = &hsw_power_well_ops,
4545+
.id = DISP_PW_ID_NONE,
4546+
{
4547+
.hsw.regs = &icl_ddi_power_well_regs,
4548+
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
4549+
}
4550+
},
4551+
{
4552+
.name = "DDI B IO",
4553+
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
4554+
.ops = &hsw_power_well_ops,
4555+
.id = DISP_PW_ID_NONE,
4556+
{
4557+
.hsw.regs = &icl_ddi_power_well_regs,
4558+
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
4559+
}
4560+
},
4561+
{
4562+
.name = "DDI IO TC1",
4563+
.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
4564+
.ops = &hsw_power_well_ops,
4565+
.id = DISP_PW_ID_NONE,
4566+
{
4567+
.hsw.regs = &icl_ddi_power_well_regs,
4568+
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
4569+
},
4570+
},
4571+
{
4572+
.name = "DDI IO TC2",
4573+
.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
4574+
.ops = &hsw_power_well_ops,
4575+
.id = DISP_PW_ID_NONE,
4576+
{
4577+
.hsw.regs = &icl_ddi_power_well_regs,
4578+
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
4579+
},
4580+
},
4581+
{
4582+
.name = "AUX A",
4583+
.domains = TGL_AUX_A_IO_POWER_DOMAINS,
4584+
.ops = &icl_aux_power_well_ops,
4585+
.id = DISP_PW_ID_NONE,
4586+
{
4587+
.hsw.regs = &icl_aux_power_well_regs,
4588+
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
4589+
},
4590+
},
4591+
{
4592+
.name = "AUX B",
4593+
.domains = TGL_AUX_B_IO_POWER_DOMAINS,
4594+
.ops = &icl_aux_power_well_ops,
4595+
.id = DISP_PW_ID_NONE,
4596+
{
4597+
.hsw.regs = &icl_aux_power_well_regs,
4598+
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
4599+
},
4600+
},
4601+
{
4602+
.name = "AUX USBC1",
4603+
.domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
4604+
.ops = &icl_aux_power_well_ops,
4605+
.id = DISP_PW_ID_NONE,
4606+
{
4607+
.hsw.regs = &icl_aux_power_well_regs,
4608+
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
4609+
.hsw.is_tc_tbt = false,
4610+
},
4611+
},
4612+
{
4613+
.name = "AUX USBC2",
4614+
.domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
4615+
.ops = &icl_aux_power_well_ops,
4616+
.id = DISP_PW_ID_NONE,
4617+
{
4618+
.hsw.regs = &icl_aux_power_well_regs,
4619+
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
4620+
.hsw.is_tc_tbt = false,
4621+
},
4622+
},
4623+
{
4624+
.name = "power well 4",
4625+
.domains = TGL_PW_4_POWER_DOMAINS,
4626+
.ops = &hsw_power_well_ops,
4627+
.id = DISP_PW_ID_NONE,
4628+
{
4629+
.hsw.regs = &hsw_power_well_regs,
4630+
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
4631+
.hsw.has_fuses = true,
4632+
.hsw.irq_pipe_mask = BIT(PIPE_C),
4633+
}
4634+
},
4635+
{
4636+
.name = "power well 5",
4637+
.domains = TGL_PW_5_POWER_DOMAINS,
4638+
.ops = &hsw_power_well_ops,
4639+
.id = DISP_PW_ID_NONE,
4640+
{
4641+
.hsw.regs = &hsw_power_well_regs,
4642+
.hsw.idx = TGL_PW_CTL_IDX_PW_5,
4643+
.hsw.has_fuses = true,
4644+
.hsw.irq_pipe_mask = BIT(PIPE_D),
4645+
},
4646+
},
4647+
};
4648+
44484649
static const struct i915_power_well_desc xelpd_power_wells[] = {
44494650
{
44504651
.name = "always-on",
@@ -4929,7 +5130,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
49295130
err = 0;
49305131
} else if (DISPLAY_VER(dev_priv) >= 13) {
49315132
err = set_power_wells(power_domains, xelpd_power_wells);
4932-
} else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
5133+
} else if (IS_DG1(dev_priv)) {
5134+
err = set_power_wells(power_domains, dg1_power_wells);
5135+
} else if (IS_ALDERLAKE_S(dev_priv)) {
49335136
err = set_power_wells_mask(power_domains, tgl_power_wells,
49345137
BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
49355138
} else if (IS_ROCKETLAKE(dev_priv)) {

‎drivers/gpu/drm/i915/display/intel_display_power.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,8 @@ enum intel_display_power_domain {
7676
POWER_DOMAIN_PORT_CRT,
7777
POWER_DOMAIN_PORT_OTHER,
7878
POWER_DOMAIN_VGA,
79-
POWER_DOMAIN_AUDIO,
79+
POWER_DOMAIN_AUDIO_MMIO,
80+
POWER_DOMAIN_AUDIO_PLAYBACK,
8081
POWER_DOMAIN_AUX_A,
8182
POWER_DOMAIN_AUX_B,
8283
POWER_DOMAIN_AUX_C,

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