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bebarinobebarino
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Merge branches 'clk-renesas', 'clk-cleanup' and 'clk-determine-divider' into clk-next
 - Migrate some clk drivers to clk_divider_ops.determine_rate * clk-renesas: clk: renesas: Make CLK_R9A06G032 invisible clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2 dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock clk: renesas: r9a07g044: Add clock and reset entries for ADC clk: renesas: r9a07g044: Add clock and reset entries for CANFD clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch] clk: renesas: r9a07g044: Add GPIO clock and reset entries clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries clk: renesas: r9a07g044: Add USB clocks/resets clk: renesas: r9a07g044: Add DMAC clocks/resets clk: renesas: r9a07g044: Add I2C clocks/resets clk: renesas: r8a779a0: Add the DSI clocks clk: renesas: r8a779a0: Add the DU clock clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() clk: renesas: rzg2l: Avoid mixing error pointers and NULL clk: renesas: rzg2l: Fix a double free on error clk: renesas: rzg2l: Fix return value and unused assignment clk: renesas: rzg2l: Remove unneeded semicolon * clk-cleanup: clk: palmas: Add a missing SPDX license header clk: Align provider-specific CLK_* bit definitions * clk-determine-divider: clk: stm32mp1: Switch to clk_divider.determine_rate clk: stm32h7: Switch to clk_divider.determine_rate clk: stm32f4: Switch to clk_divider.determine_rate clk: bcm2835: Switch to clk_divider.determine_rate clk: divider: Implement and wire up .determine_rate by default
4 parents 4990d8c + a1cde1f + 28fc39f + 23a57ee commit 7110569

18 files changed

+132
-60
lines changed

‎drivers/clk/bcm/clk-bcm2835.c

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -805,11 +805,10 @@ static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
805805
return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
806806
}
807807

808-
static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
809-
unsigned long rate,
810-
unsigned long *parent_rate)
808+
static int bcm2835_pll_divider_determine_rate(struct clk_hw *hw,
809+
struct clk_rate_request *req)
811810
{
812-
return clk_divider_ops.round_rate(hw, rate, parent_rate);
811+
return clk_divider_ops.determine_rate(hw, req);
813812
}
814813

815814
static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
@@ -901,7 +900,7 @@ static const struct clk_ops bcm2835_pll_divider_clk_ops = {
901900
.unprepare = bcm2835_pll_divider_off,
902901
.recalc_rate = bcm2835_pll_divider_get_rate,
903902
.set_rate = bcm2835_pll_divider_set_rate,
904-
.round_rate = bcm2835_pll_divider_round_rate,
903+
.determine_rate = bcm2835_pll_divider_determine_rate,
905904
.debug_init = bcm2835_pll_divider_debug_init,
906905
};
907906

‎drivers/clk/clk-divider.c

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -446,6 +446,27 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
446446
divider->width, divider->flags);
447447
}
448448

449+
static int clk_divider_determine_rate(struct clk_hw *hw,
450+
struct clk_rate_request *req)
451+
{
452+
struct clk_divider *divider = to_clk_divider(hw);
453+
454+
/* if read only, just return current value */
455+
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
456+
u32 val;
457+
458+
val = clk_div_readl(divider) >> divider->shift;
459+
val &= clk_div_mask(divider->width);
460+
461+
return divider_ro_determine_rate(hw, req, divider->table,
462+
divider->width,
463+
divider->flags, val);
464+
}
465+
466+
return divider_determine_rate(hw, req, divider->table, divider->width,
467+
divider->flags);
468+
}
469+
449470
int divider_get_val(unsigned long rate, unsigned long parent_rate,
450471
const struct clk_div_table *table, u8 width,
451472
unsigned long flags)
@@ -501,13 +522,15 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
501522
const struct clk_ops clk_divider_ops = {
502523
.recalc_rate = clk_divider_recalc_rate,
503524
.round_rate = clk_divider_round_rate,
525+
.determine_rate = clk_divider_determine_rate,
504526
.set_rate = clk_divider_set_rate,
505527
};
506528
EXPORT_SYMBOL_GPL(clk_divider_ops);
507529

508530
const struct clk_ops clk_divider_ro_ops = {
509531
.recalc_rate = clk_divider_recalc_rate,
510532
.round_rate = clk_divider_round_rate,
533+
.determine_rate = clk_divider_determine_rate,
511534
};
512535
EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
513536

‎drivers/clk/clk-palmas.c

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
// SPDX-License-Identifier: GPL-2.0
12
/*
23
* Clock driver for Palmas device.
34
*
@@ -6,15 +7,6 @@
67
*
78
* Author: Laxman Dewangan <[email protected]>
89
* Peter Ujfalusi <[email protected]>
9-
*
10-
* This program is free software; you can redistribute it and/or
11-
* modify it under the terms of the GNU General Public License as
12-
* published by the Free Software Foundation version 2.
13-
*
14-
* This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
15-
* whether express or implied; without even the implied warranty of
16-
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17-
* General Public License for more details.
1810
*/
1911

2012
#include <linux/clk.h>

‎drivers/clk/clk-stm32f4.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -709,10 +709,10 @@ static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw,
709709
return clk_divider_ops.recalc_rate(hw, parent_rate);
710710
}
711711

712-
static long stm32f4_pll_div_round_rate(struct clk_hw *hw, unsigned long rate,
713-
unsigned long *prate)
712+
static int stm32f4_pll_div_determine_rate(struct clk_hw *hw,
713+
struct clk_rate_request *req)
714714
{
715-
return clk_divider_ops.round_rate(hw, rate, prate);
715+
return clk_divider_ops.determine_rate(hw, req);
716716
}
717717

718718
static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -738,7 +738,7 @@ static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
738738

739739
static const struct clk_ops stm32f4_pll_div_ops = {
740740
.recalc_rate = stm32f4_pll_div_recalc_rate,
741-
.round_rate = stm32f4_pll_div_round_rate,
741+
.determine_rate = stm32f4_pll_div_determine_rate,
742742
.set_rate = stm32f4_pll_div_set_rate,
743743
};
744744

‎drivers/clk/clk-stm32h7.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -845,10 +845,10 @@ static unsigned long odf_divider_recalc_rate(struct clk_hw *hw,
845845
return clk_divider_ops.recalc_rate(hw, parent_rate);
846846
}
847847

848-
static long odf_divider_round_rate(struct clk_hw *hw, unsigned long rate,
849-
unsigned long *prate)
848+
static int odf_divider_determine_rate(struct clk_hw *hw,
849+
struct clk_rate_request *req)
850850
{
851-
return clk_divider_ops.round_rate(hw, rate, prate);
851+
return clk_divider_ops.determine_rate(hw, req);
852852
}
853853

854854
static int odf_divider_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -875,7 +875,7 @@ static int odf_divider_set_rate(struct clk_hw *hw, unsigned long rate,
875875

876876
static const struct clk_ops odf_divider_ops = {
877877
.recalc_rate = odf_divider_recalc_rate,
878-
.round_rate = odf_divider_round_rate,
878+
.determine_rate = odf_divider_determine_rate,
879879
.set_rate = odf_divider_set_rate,
880880
};
881881

‎drivers/clk/clk-stm32mp1.c

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1076,14 +1076,10 @@ static int clk_divider_rtc_set_rate(struct clk_hw *hw, unsigned long rate,
10761076

10771077
static int clk_divider_rtc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
10781078
{
1079-
unsigned long best_parent_rate = req->best_parent_rate;
1079+
if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC))
1080+
return clk_divider_ops.determine_rate(hw, req);
10801081

1081-
if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC)) {
1082-
req->rate = clk_divider_ops.round_rate(hw, req->rate, &best_parent_rate);
1083-
req->best_parent_rate = best_parent_rate;
1084-
} else {
1085-
req->rate = best_parent_rate;
1086-
}
1082+
req->rate = req->best_parent_rate;
10871083

10881084
return 0;
10891085
}

‎drivers/clk/renesas/Kconfig

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -153,9 +153,7 @@ config CLK_R8A779A0
153153
select CLK_RENESAS_CPG_MSSR
154154

155155
config CLK_R9A06G032
156-
bool "Renesas R9A06G032 clock driver"
157-
help
158-
This is a driver for R9A06G032 clocks
156+
bool "RZ/N1D clock support" if COMPILE_TEST
159157

160158
config CLK_R9A07G044
161159
bool "RZ/G2L clock support" if COMPILE_TEST

‎drivers/clk/renesas/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
3737
obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
3838
obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
3939
obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
40-
obj-$(CONFIG_CLK_RZG2L) += renesas-rzg2l-cpg.o
40+
obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
4141

4242
# Generic
4343
obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o

‎drivers/clk/renesas/r8a774a1-cpg-mssr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -210,7 +210,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
210210
DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2),
211211
DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
212212
DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
213-
DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
213+
DEF_MOD("iic-pmic", 926, R8A774A1_CLK_CP),
214214
DEF_MOD("i2c4", 927, R8A774A1_CLK_S0D6),
215215
DEF_MOD("i2c3", 928, R8A774A1_CLK_S0D6),
216216
DEF_MOD("i2c2", 929, R8A774A1_CLK_S3D2),

‎drivers/clk/renesas/r8a774b1-cpg-mssr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -206,7 +206,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
206206
DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2),
207207
DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
208208
DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
209-
DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
209+
DEF_MOD("iic-pmic", 926, R8A774B1_CLK_CP),
210210
DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6),
211211
DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6),
212212
DEF_MOD("i2c2", 929, R8A774B1_CLK_S3D2),

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