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lucasdemarchilucasdemarchi
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drm/i915: rename/remove CNL registers
Remove registers that are not used anymore due to CNL removal and rename those that are. Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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-146
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+48
-146
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‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 47 additions & 145 deletions
Original file line numberDiff line numberDiff line change
@@ -1877,7 +1877,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
18771877
#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
18781878

18791879
/*
1880-
* CNL/ICL Port/COMBO-PHY Registers
1880+
* ICL Port/COMBO-PHY Registers
18811881
*/
18821882
#define _ICL_COMBOPHY_A 0x162000
18831883
#define _ICL_COMBOPHY_B 0x6C000
@@ -1891,11 +1891,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
18911891
_RKL_COMBOPHY_D, \
18921892
_ADL_COMBOPHY_E)
18931893

1894-
/* CNL/ICL Port CL_DW registers */
1894+
/* ICL Port CL_DW registers */
18951895
#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
18961896
4 * (dw))
18971897

1898-
#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
18991898
#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
19001899
#define CL_POWER_DOWN_ENABLE (1 << 4)
19011900
#define SUS_CLOCK_CONFIG (3 << 0)
@@ -1920,19 +1919,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
19201919
#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
19211920
#define ICL_LANE_ENABLE_AUX (1 << 0)
19221921

1923-
/* CNL/ICL Port COMP_DW registers */
1922+
/* ICL Port COMP_DW registers */
19241923
#define _ICL_PORT_COMP 0x100
19251924
#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
19261925
_ICL_PORT_COMP + 4 * (dw))
19271926

1928-
#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
19291927
#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
19301928
#define COMP_INIT (1 << 31)
19311929

1932-
#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
19331930
#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
19341931

1935-
#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
19361932
#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
19371933
#define PROCESS_INFO_DOT_0 (0 << 26)
19381934
#define PROCESS_INFO_DOT_1 (1 << 26)
@@ -1948,38 +1944,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
19481944
#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
19491945
#define IREFGEN (1 << 24)
19501946

1951-
#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
19521947
#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
19531948

1954-
#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
19551949
#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
19561950

1957-
/* CNL/ICL Port PCS registers */
1958-
#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
1959-
#define _CNL_PORT_PCS_DW1_GRP_B 0x162384
1960-
#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
1961-
#define _CNL_PORT_PCS_DW1_GRP_D 0x162B84
1962-
#define _CNL_PORT_PCS_DW1_GRP_F 0x162A04
1963-
#define _CNL_PORT_PCS_DW1_LN0_AE 0x162404
1964-
#define _CNL_PORT_PCS_DW1_LN0_B 0x162604
1965-
#define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
1966-
#define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
1967-
#define _CNL_PORT_PCS_DW1_LN0_F 0x162804
1968-
#define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \
1969-
_CNL_PORT_PCS_DW1_GRP_AE, \
1970-
_CNL_PORT_PCS_DW1_GRP_B, \
1971-
_CNL_PORT_PCS_DW1_GRP_C, \
1972-
_CNL_PORT_PCS_DW1_GRP_D, \
1973-
_CNL_PORT_PCS_DW1_GRP_AE, \
1974-
_CNL_PORT_PCS_DW1_GRP_F))
1975-
#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \
1976-
_CNL_PORT_PCS_DW1_LN0_AE, \
1977-
_CNL_PORT_PCS_DW1_LN0_B, \
1978-
_CNL_PORT_PCS_DW1_LN0_C, \
1979-
_CNL_PORT_PCS_DW1_LN0_D, \
1980-
_CNL_PORT_PCS_DW1_LN0_AE, \
1981-
_CNL_PORT_PCS_DW1_LN0_F))
1982-
1951+
/* ICL Port PCS registers */
19831952
#define _ICL_PORT_PCS_AUX 0x300
19841953
#define _ICL_PORT_PCS_GRP 0x600
19851954
#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
@@ -1998,34 +1967,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
19981967
#define LATENCY_OPTIM_MASK (0x3 << 2)
19991968
#define LATENCY_OPTIM_VAL(x) ((x) << 2)
20001969

2001-
/* CNL/ICL Port TX registers */
2002-
#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
2003-
#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
2004-
#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
2005-
#define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0
2006-
#define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40
2007-
#define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440
2008-
#define _CNL_PORT_TX_B_LN0_OFFSET 0x162640
2009-
#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
2010-
#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
2011-
#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
2012-
#define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \
2013-
_CNL_PORT_TX_AE_GRP_OFFSET, \
2014-
_CNL_PORT_TX_B_GRP_OFFSET, \
2015-
_CNL_PORT_TX_B_GRP_OFFSET, \
2016-
_CNL_PORT_TX_D_GRP_OFFSET, \
2017-
_CNL_PORT_TX_AE_GRP_OFFSET, \
2018-
_CNL_PORT_TX_F_GRP_OFFSET) + \
2019-
4 * (dw))
2020-
#define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \
2021-
_CNL_PORT_TX_AE_LN0_OFFSET, \
2022-
_CNL_PORT_TX_B_LN0_OFFSET, \
2023-
_CNL_PORT_TX_B_LN0_OFFSET, \
2024-
_CNL_PORT_TX_D_LN0_OFFSET, \
2025-
_CNL_PORT_TX_AE_LN0_OFFSET, \
2026-
_CNL_PORT_TX_F_LN0_OFFSET) + \
2027-
4 * (dw))
2028-
1970+
/* ICL Port TX registers */
20291971
#define _ICL_PORT_TX_AUX 0x380
20301972
#define _ICL_PORT_TX_GRP 0x680
20311973
#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
@@ -2037,8 +1979,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
20371979
#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
20381980
_ICL_PORT_TX_LN(ln) + 4 * (dw))
20391981

2040-
#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
2041-
#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
20421982
#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
20431983
#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
20441984
#define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
@@ -2051,13 +1991,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
20511991
#define RCOMP_SCALAR(x) ((x) << 0)
20521992
#define RCOMP_SCALAR_MASK (0xFF << 0)
20531993

2054-
#define _CNL_PORT_TX_DW4_LN0_AE 0x162450
2055-
#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
2056-
#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
2057-
#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
2058-
#define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
2059-
((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
2060-
_CNL_PORT_TX_DW4_LN0_AE)))
20611994
#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
20621995
#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
20631996
#define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
@@ -2070,8 +2003,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
20702003
#define CURSOR_COEFF(x) ((x) << 0)
20712004
#define CURSOR_COEFF_MASK (0x3F << 0)
20722005

2073-
#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
2074-
#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
20752006
#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
20762007
#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
20772008
#define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
@@ -2083,8 +2014,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
20832014
#define RTERM_SELECT(x) ((x) << 3)
20842015
#define RTERM_SELECT_MASK (0x7 << 3)
20852016

2086-
#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
2087-
#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
20882017
#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
20892018
#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
20902019
#define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
@@ -8191,7 +8120,6 @@ enum {
81918120
#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
81928121

81938122
#define CHICKEN_MISC_2 _MMIO(0x42084)
8194-
#define CNL_COMP_PWR_DOWN (1 << 23)
81958123
#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
81968124
#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
81978125
#define GLK_CL2_PWR_DOWN (1 << 12)
@@ -8231,7 +8159,7 @@ enum {
82318159
[TRANSCODER_D] = _CHICKEN_TRANS_D))
82328160
#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
82338161
#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
8234-
#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK and CNL+ */
8162+
#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
82358163
#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
82368164
#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
82378165
#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
@@ -8298,7 +8226,6 @@ enum {
82988226
#define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
82998227
#define ICL_DELAY_PMRSP (1 << 22)
83008228
#define MASK_WAKEMEM (1 << 13)
8301-
#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
83028229

83038230
#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
83048231
#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
@@ -8319,10 +8246,9 @@ enum {
83198246
#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
83208247
#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
83218248
#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
8322-
#define CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
8249+
#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
83238250

83248251
#define SKL_DSSM _MMIO(0x51004)
8325-
#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
83268252
#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
83278253
#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
83288254
#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
@@ -8421,7 +8347,6 @@ enum {
84218347

84228348
/* GEN8 chicken */
84238349
#define HDC_CHICKEN0 _MMIO(0x7300)
8424-
#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
84258350
#define ICL_HDC_MODE _MMIO(0xE5F4)
84268351
#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
84278352
#define HDC_FENCE_DEST_SLM_DISABLE (1 << 14)
@@ -9602,7 +9527,6 @@ enum {
96029527
#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
96039528
#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
96049529
#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
9605-
#define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4)
96069530
#define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
96079531

96089532
#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
@@ -9783,15 +9707,12 @@ enum {
97839707
/* HSW/BDW power well */
97849708
#define HSW_PW_CTL_IDX_GLOBAL 15
97859709

9786-
/* SKL/BXT/GLK/CNL power wells */
9710+
/* SKL/BXT/GLK power wells */
97879711
#define SKL_PW_CTL_IDX_PW_2 15
97889712
#define SKL_PW_CTL_IDX_PW_1 14
9789-
#define CNL_PW_CTL_IDX_AUX_F 12
9790-
#define CNL_PW_CTL_IDX_AUX_D 11
97919713
#define GLK_PW_CTL_IDX_AUX_C 10
97929714
#define GLK_PW_CTL_IDX_AUX_B 9
97939715
#define GLK_PW_CTL_IDX_AUX_A 8
9794-
#define CNL_PW_CTL_IDX_DDI_F 6
97959716
#define SKL_PW_CTL_IDX_DDI_D 4
97969717
#define SKL_PW_CTL_IDX_DDI_C 3
97979718
#define SKL_PW_CTL_IDX_DDI_B 2
@@ -10189,11 +10110,11 @@ enum skl_power_gate {
1018910110
#define TRANS_DDI_BPC_10 (1 << 20)
1019010111
#define TRANS_DDI_BPC_6 (2 << 20)
1019110112
#define TRANS_DDI_BPC_12 (3 << 20)
10192-
#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) /* bdw-cnl */
10113+
#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
1019310114
#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
1019410115
#define TRANS_DDI_PVSYNC (1 << 17)
1019510116
#define TRANS_DDI_PHSYNC (1 << 16)
10196-
#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) /* bdw-cnl */
10117+
#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
1019710118
#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
1019810119
#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
1019910120
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
@@ -10552,17 +10473,6 @@ enum skl_power_gate {
1055210473
#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
1055310474
#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
1055410475

10555-
/*
10556-
* CNL Clocks
10557-
*/
10558-
#define DPCLKA_CFGCR0 _MMIO(0x6C200)
10559-
#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
10560-
(port) + 10))
10561-
#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
10562-
(port) * 2)
10563-
#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
10564-
#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
10565-
1056610476
/* ICL Clocks */
1056710477
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
1056810478
#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
@@ -10800,60 +10710,52 @@ enum skl_power_gate {
1080010710
_MG_PLL_TDC_COLDST_BIAS_PORT1, \
1080110711
_MG_PLL_TDC_COLDST_BIAS_PORT2)
1080210712

10803-
#define _CNL_DPLL0_CFGCR0 0x6C000
10804-
#define _CNL_DPLL1_CFGCR0 0x6C080
10805-
#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
10806-
#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
10807-
#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
10808-
#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
10809-
#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
10810-
#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
10811-
#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
10812-
#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
10813-
#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
10814-
#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
10815-
#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
10816-
#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
10817-
#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
10818-
#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
10819-
#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
10820-
#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
10821-
#define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
10822-
10823-
#define _CNL_DPLL0_CFGCR1 0x6C004
10824-
#define _CNL_DPLL1_CFGCR1 0x6C084
10825-
#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
10826-
#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
10827-
#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
10828-
#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
10829-
#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
10830-
#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
10831-
#define DPLL_CFGCR1_KDIV_SHIFT (6)
10832-
#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
10833-
#define DPLL_CFGCR1_KDIV_1 (1 << 6)
10834-
#define DPLL_CFGCR1_KDIV_2 (2 << 6)
10835-
#define DPLL_CFGCR1_KDIV_3 (4 << 6)
10836-
#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
10837-
#define DPLL_CFGCR1_PDIV_SHIFT (2)
10838-
#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
10839-
#define DPLL_CFGCR1_PDIV_2 (1 << 2)
10840-
#define DPLL_CFGCR1_PDIV_3 (2 << 2)
10841-
#define DPLL_CFGCR1_PDIV_5 (4 << 2)
10842-
#define DPLL_CFGCR1_PDIV_7 (8 << 2)
10843-
#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
10844-
#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
10845-
#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
10846-
#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
10847-
1084810713
#define _ICL_DPLL0_CFGCR0 0x164000
1084910714
#define _ICL_DPLL1_CFGCR0 0x164080
1085010715
#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
1085110716
_ICL_DPLL1_CFGCR0)
10717+
#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
10718+
#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
10719+
#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
10720+
#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
10721+
#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
10722+
#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
10723+
#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
10724+
#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
10725+
#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
10726+
#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
10727+
#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
10728+
#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
10729+
#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
10730+
#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
10731+
#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
10732+
#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
1085210733

1085310734
#define _ICL_DPLL0_CFGCR1 0x164004
1085410735
#define _ICL_DPLL1_CFGCR1 0x164084
1085510736
#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
1085610737
_ICL_DPLL1_CFGCR1)
10738+
#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
10739+
#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
10740+
#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
10741+
#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
10742+
#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
10743+
#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
10744+
#define DPLL_CFGCR1_KDIV_SHIFT (6)
10745+
#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
10746+
#define DPLL_CFGCR1_KDIV_1 (1 << 6)
10747+
#define DPLL_CFGCR1_KDIV_2 (2 << 6)
10748+
#define DPLL_CFGCR1_KDIV_3 (4 << 6)
10749+
#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
10750+
#define DPLL_CFGCR1_PDIV_SHIFT (2)
10751+
#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
10752+
#define DPLL_CFGCR1_PDIV_2 (1 << 2)
10753+
#define DPLL_CFGCR1_PDIV_3 (2 << 2)
10754+
#define DPLL_CFGCR1_PDIV_5 (4 << 2)
10755+
#define DPLL_CFGCR1_PDIV_7 (8 << 2)
10756+
#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
10757+
#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
10758+
#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
1085710759

1085810760
#define _TGL_DPLL0_CFGCR0 0x164284
1085910761
#define _TGL_DPLL1_CFGCR0 0x16428C

‎drivers/gpu/drm/i915/intel_device_info.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -367,7 +367,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
367367
info->display.has_dmc = 0;
368368

369369
if (DISPLAY_VER(dev_priv) >= 10 &&
370-
(dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
370+
(dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
371371
info->display.has_dsc = 0;
372372
}
373373

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